Lines Matching +full:multi +full:- +full:function
1 The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
2 pins (mpp) to a specific function.
4 be used for a specific device or function. Each node requires one or more
5 mpp pins or group of pins and a mpp function common to all pins.
8 - compatible: "marvell,mvebu-pinctrl",
9 "marvell,ap806-pinctrl",
10 "marvell,armada-7k-pinctrl",
11 "marvell,armada-8k-cpm-pinctrl",
12 "marvell,armada-8k-cps-pinctrl"
13 - bank-name: A string defining the pinc controller bank name
14 - reg: A pair of values defining the pin controller base address
16 - pin-count: Numeric value defining the amount of multi purpose pins
18 - max-func: Numeric value defining the maximum function value for
20 - pin-func: Array of pin function values for every pin in the bank.
21 When the function value for a specific pin equal 0xFF,
22 the pin configuration is skipped and a default function
31 config-space {
33 compatible = "marvell,mvebu-pinctrl",
34 "marvell,ap806-pinctrl";
35 bank-name ="apn-806";
37 pin-count = <20>;
38 max-func = <3>;
40 * SPI0 [0-3]
41 * I2C0 [4-5]
45 pin-func = < 3 3 3 3 3 3 0 0 0 0
51 cp110-master {
52 config-space {
54 compatible = "marvell,mvebu-pinctrl",
55 "marvell,armada-7k-pinctrl",
56 "marvell,armada-8k-cpm-pinctrl";
57 bank-name ="cp0-110";
59 pin-count = <63>;
60 max-func = <0xf>;
62 * [0-31] = 0xff: Keep default CP0_shared_pins:
69 * [35-36] GPIO
70 * [37-38] I2C
71 * [40-41] SATA[0/1]_PRESENT_ACTIVEn
72 * [42-43] XSMI
73 * [44-55] RGMII1
74 * [56-62] SD
77 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
88 cp110-slave {
89 config-space {
91 compatible = "marvell,mvebu-pinctrl",
92 "marvell,armada-8k-cps-pinctrl";
93 bank-name ="cp1-110";
95 pin-count = <63>;
96 max-func = <0xf>;
98 * [0-11] RGMII0
100 * [32-62] = 0xff: Keep default CP1_shared_pins:
103 pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3