| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | fsl,ls-scfg-msi.txt | 1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
6 Layerscape PCIe MSI controller block such as:
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
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| H A D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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| H A D | loongson,pch-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
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| H A D | hisilicon,mbigen-v2.txt | 6 MBI is kind of msi interrupt only used on Non-PCI devices.
12 Non-pci devices can connect to mbigen and generate the
18 -------------------------------------------
19 - compatible: Should be "hisilicon,mbigen-v2"
21 - reg: Specifies the base physical address and size of the Mbigen
25 ------------------------------------------
26 - interrupt controller: Identifies the node as an interrupt controller
28 - msi-parent: Specifies the MSI controller this mbigen use.
29 For more detail information,please refer to the generic msi-parent binding in
30 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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| /openbmc/linux/drivers/pci/msi/ |
| H A D | irqdomain.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI) - irqdomain support
9 #include "msi.h"
15 domain = dev_get_msi_domain(&dev->dev); in pci_msi_setup_msi_irqs()
17 return msi_domain_alloc_irqs_all_locked(&dev->dev, MSI_DEFAULT_DOMAIN, nvec); in pci_msi_setup_msi_irqs()
26 domain = dev_get_msi_domain(&dev->dev); in pci_msi_teardown_msi_irqs()
28 msi_domain_free_irqs_all_locked(&dev->dev, MSI_DEFAULT_DOMAIN); in pci_msi_teardown_msi_irqs()
31 msi_free_msi_descs(&dev->dev); in pci_msi_teardown_msi_irqs()
36 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
37 * @irq_data: Pointer to interrupt data of the MSI interrupt
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| /openbmc/linux/drivers/base/ |
| H A D | platform-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MSI framework for platform devices
13 #include <linux/msi.h>
17 #define MAX_DEV_MSIS (1 << (32 - DEV_ID_SHIFT))
21 * and the callback to write the MSI message.
36 * Convert an msi_desc to a globaly unique identifier (per-device
41 u32 devid = desc->dev->msi.data->platform_data->devid; in platform_msi_calc_hwirq()
43 return (devid << (32 - DEV_ID_SHIFT)) | desc->msi_index; in platform_msi_calc_hwirq()
48 arg->desc = desc; in platform_msi_set_desc()
49 arg->hwirq = platform_msi_calc_hwirq(desc); in platform_msi_set_desc()
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| /openbmc/linux/kernel/irq/ |
| H A D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/msi.h>
23 * struct msi_ctrl - MSI internal management control structure
28 * than the range due to PCI/multi-MSI.
38 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
48 * msi_alloc_desc - Allocate an initialized msi_desc
66 desc->dev = dev; in msi_alloc_desc()
67 desc->nvec_used = nvec; in msi_alloc_desc()
69 desc->affinity = kmemdup(affinity, nvec * sizeof(*desc->affinity), GFP_KERNEL); in msi_alloc_desc()
70 if (!desc->affinity) { in msi_alloc_desc()
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | altera-pcie-msi.txt | 1 * Altera PCIe MSI controller
4 - compatible: should contain "altr,msi-1.0"
5 - reg: specifies the physical base address of the controller and
7 - reg-names: must include the following entries:
10 - interrupts: specifies the interrupt source of the parent interrupt
12 parent interrupt controller.
13 - num-vectors: number of vectors, range 1 to 32.
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
19 compatible = "altr,msi-1.0";
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| H A D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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| H A D | microchip,pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
23 reg-names:
25 - const: cfg
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| H A D | apple,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
22 the standard "reset-gpios" and "max-link-speed" properties appear on
34 - enum:
35 - apple,t8103-pcie
36 - apple,t8112-pcie
37 - apple,t6000-pcie
38 - const: apple,pcie
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| H A D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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| /openbmc/linux/include/linux/ |
| H A D | msi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
30 #include <asm/msi.h>
56 * msi_msg - Representation of a MSI message
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-loongson-pch-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
43 .name = "PCH PCI MSI",
54 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
56 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
59 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
60 return -ENOSPC; in pch_msi_allocate_hwirq()
63 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
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| H A D | irq-gic-v3-its-platform-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
9 #include <linux/msi.h>
14 .name = "ITS-pMSI",
22 /* Suck the DeviceID out of the msi-parent property */ in of_pmsi_get_dev_id()
26 ret = of_parse_phandle_with_args(dev->of_node, in of_pmsi_get_dev_id()
27 "msi-parent", "#msi-cells", in of_pmsi_get_dev_id()
31 return -EINVAL; in of_pmsi_get_dev_id()
43 return -1; in iort_pmsi_get_dev_id()
53 msi_info = msi_get_domain_info(domain->parent); in its_pmsi_prepare()
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| H A D | irq-gic-v3-its-pci-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
9 #include <linux/msi.h>
27 .name = "ITS-MSI",
35 int msi, msix, *count = data; in its_pci_msi_vec_count() local
37 msi = max(pci_msi_vec_count(pdev), 0); in its_pci_msi_vec_count()
39 *count += max(msi, msix); in its_pci_msi_vec_count()
61 return -EINVAL; in its_pci_msi_prepare()
63 msi_info = msi_get_domain_info(domain->parent); in its_pci_msi_prepare()
74 if (alias_dev->subordinate) in its_pci_msi_prepare()
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| H A D | irq-gic-v2m.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
32 * [25:16] lowest SPI assigned to MSI
34 * [9:0] Numer of SPIs assigned to MSI
50 /* APM X-Gene with GICv2m MSI_IIDR register value */
71 unsigned long *bm; /* MSI vector bitmap */
88 .name = "MSI",
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| H A D | irq-ls-scfg-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale SCFG MSI(-X) support
12 #include <linux/msi.h>
48 struct irq_domain *parent; member
60 .name = "MSI",
76 if (p && strncmp(p, "no-affinity", 11) == 0) in early_parse_ls_scfg_msi()
89 msg->address_hi = upper_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
90 msg->address_lo = lower_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
91 msg->data = data->hwirq; in ls_scfg_msi_compose_msg()
97 msg->data |= cpumask_first(mask); in ls_scfg_msi_compose_msg()
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| /openbmc/linux/drivers/of/ |
| H A D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
31 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
50 * of_irq_find_parent - Given a device node, find its interrupt parent node
53 * Return: A pointer to the interrupt parent node, or NULL if the interrupt
54 * parent could not be determined.
59 phandle parent; in of_irq_find_parent() local
65 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
71 p = of_find_node_by_phandle(parent); in of_irq_find_parent()
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| /openbmc/linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-ap810-ap0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
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| H A D | armada-ap80x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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| /openbmc/linux/drivers/bus/fsl-mc/ |
| H A D | fsl-mc-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale Management Complex (MC) bus driver MSI support
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
13 #include <linux/msi.h>
16 #include "fsl-mc-private.h"
20 * Generate a unique ID identifying the interrupt (only used within the MSI
30 return (irq_hw_number_t)(desc->msi_index + (dev->icid * 10000)); in fsl_mc_domain_calc_hwirq()
36 arg->desc = desc; in fsl_mc_msi_set_desc()
37 arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), in fsl_mc_msi_set_desc()
46 struct msi_domain_ops *ops = info->ops; in fsl_mc_msi_update_dom_ops()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | armada-ap806.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 /dts-v1/;
53 compatible = "marvell,armada-ap806";
54 #address-cells = <2>;
55 #size-cells = <2>;
63 compatible = "arm,psci-0.2";
67 reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
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| /openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/ |
| H A D | ns2.dtsi | 35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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| /openbmc/linux/drivers/pci/controller/ |
| H A D | pcie-rcar-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
24 #include <linux/msi.h>
33 #include "pcie-rcar.h"
49 struct rcar_msi msi; member
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