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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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H A Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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H A Dxilinx-versal-cpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
23 - description: CPM system level control and status registers.
24 - description: Configuration space region and bridge registers.
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H A Dmicrochip,pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
23 reg-names:
25 - const: cfg
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H A Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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H A Daardvark-pci.txt8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe controller can itself
17 handle MSI interrupts
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H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7278-pcie # Broadcom 7278 Arm
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H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
22 the standard "reset-gpios" and "max-link-speed" properties appear on
34 - enum:
35 - apple,t8103-pcie
36 - apple,t8112-pcie
37 - apple,t6000-pcie
38 - const: apple,pcie
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H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
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H A Dlayerscape-pcie-gen4.txt4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
20 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
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H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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H A Daltera-pcie.txt4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - #interrupt-cells: set to <1>
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/openbmc/linux/drivers/pci/msi/
H A Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
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/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
22 the set of possible ICIDs under a root DPRC and how they map to
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
35 For generic MSI bindings, see
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/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 on run-time.
18 and a unique device ID (for MSI) corresponding to a requestor ID
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
25 The MSI writes are accompanied by sideband data (Device ID).
26 The msi-map property is used to associate the devices with the
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/openbmc/u-boot/drivers/pci/
H A Dpcie_layerscape_fixup.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
27 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) in ls_pcie_next_lut_index()
28 return pcie->next_lut_index++; in ls_pcie_next_lut_index()
30 return -ENOSPC; /* LUT is full */ in ls_pcie_next_lut_index()
33 /* returns the next available streamid for pcie, -errno if failed */
39 return -EINVAL; in ls_pcie_next_streamid()
47 if (pcie->big_endian) in lut_writel()
48 out_be32(pcie->lut + offset, value); in lut_writel()
50 out_le32(pcie->lut + offset, value); in lut_writel()
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/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_irq.c1 // SPDX-License-Identifier: GPL-2.0
9 * ice_init_irq_tracker - initialize interrupt tracker
18 pf->irq_tracker.num_entries = max_vectors; in ice_init_irq_tracker()
19 pf->irq_tracker.num_static = num_static; in ice_init_irq_tracker()
20 xa_init_flags(&pf->irq_tracker.entries, XA_FLAGS_ALLOC); in ice_init_irq_tracker()
24 * ice_deinit_irq_tracker - free xarray tracker
29 xa_destroy(&pf->irq_tracker.entries); in ice_deinit_irq_tracker()
33 * ice_free_irq_res - free a block of resources
41 entry = xa_erase(&pf->irq_tracker.entries, index); in ice_free_irq_res()
46 * ice_get_irq_res - get an interrupt resource
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/openbmc/linux/drivers/of/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
31 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
33 * @index: Index of the interrupt to map
50 * of_irq_find_parent - Given a device node, find its interrupt parent node
65 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
75 } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL); in of_irq_find_parent()
82 * These interrupt controllers abuse interrupt-map for unspeakable
85 * non-sensical interrupt-map that is better left ignored.
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/openbmc/linux/virt/kvm/
H A Dirqchip.c1 // SPDX-License-Identifier: GPL-2.0-only
28 irq_rt = srcu_dereference_check(kvm->irq_routing, &kvm->irq_srcu, in kvm_irq_map_gsi()
29 lockdep_is_held(&kvm->irq_lock)); in kvm_irq_map_gsi()
30 if (irq_rt && gsi < irq_rt->nr_rt_entries) { in kvm_irq_map_gsi()
31 hlist_for_each_entry(e, &irq_rt->map[gsi], link) { in kvm_irq_map_gsi()
44 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); in kvm_irq_map_chip_pin()
45 return irq_rt->chip[irqchip][pin]; in kvm_irq_map_chip_pin()
48 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi) in kvm_send_userspace_msi() argument
52 if (!kvm_arch_irqchip_in_kernel(kvm) || (msi->flags & ~KVM_MSI_VALID_DEVID)) in kvm_send_userspace_msi()
53 return -EINVAL; in kvm_send_userspace_msi()
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
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/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dstream_id_lsch3.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015-2018 NXP
11 * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
20 * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
21 * -all legacy devices get a unique stream ID assigned and programmed in
22 * their AMQR registers by u-boot
24 * -PCIe
25 * -there is a range of stream IDs set aside for PCI in this
26 * file. U-boot will scan the PCI bus and for each device discovered:
27 * -allocate a streamID
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H A Dstream_id_lsch2.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
19 * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
20 * -all legacy devices get a unique stream ID assigned and programmed in
21 * their AMQR registers by u-boot
23 * -PCIe
24 * -there is a range of stream IDs set aside for PCI in this
25 * file. U-boot will scan the PCI bus and for each device discovered:
26 * -allocate a streamID
27 * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
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/openbmc/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
19 #include <linux/msi.h>
25 #include "pcie-mobiveil.h"
37 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
44 * mobiveil_pcie_map_bus - routine to get the configuration base of either
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
67 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
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/openbmc/linux/arch/powerpc/sysdev/
H A Dfsl_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
11 #include <linux/msi.h>
22 #include <asm/ppc-pci.h>
37 #define msi_hwirq(msi, msir_index, intr_index) \ argument
38 ((msir_index) << (msi)->srs_shift | \
39 ((intr_index) << (msi)->ibs_shift))
61 * in the cascade interrupt. So, this MSI interrupt has been acked
69 struct fsl_msi *msi_data = irqd->domain->host_data; in fsl_msi_print_chip()
73 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; in fsl_msi_print_chip()
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