Home
last modified time | relevance | path

Searched full:mpll (Results 1 – 25 of 126) sorted by relevance

123456

/openbmc/linux/drivers/clk/mstar/
H A Dclk-msc313-mpll.c3 * MStar MSC313 MPLL driver
47 struct msc313_mpll *mpll = to_mpll(hw); in msc313_mpll_recalc_rate() local
51 regmap_field_read(mpll->input_div, &input_div); in msc313_mpll_recalc_rate()
52 regmap_field_read(mpll->output_div, &output_div); in msc313_mpll_recalc_rate()
53 regmap_field_read(mpll->loop_div_first, &loop_first); in msc313_mpll_recalc_rate()
54 regmap_field_read(mpll->loop_div_second, &loop_second); in msc313_mpll_recalc_rate()
74 struct msc313_mpll *mpll; in msc313_mpll_probe() local
82 mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL); in msc313_mpll_probe()
83 if (!mpll) in msc313_mpll_probe()
94 mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first); in msc313_mpll_probe()
[all …]
H A DKconfig10 bool "MStar MPLL driver"
15 Support for the MPLL PLL and dividers block present on
/openbmc/linux/drivers/clk/meson/
H A Dclk-mpll.c9 * scaling capabilities. MPLL rates are calculated as:
19 #include "clk-mpll.h"
79 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_recalc_rate() local
83 sdm = meson_parm_read(clk->map, &mpll->sdm); in mpll_recalc_rate()
84 n2 = meson_parm_read(clk->map, &mpll->n2); in mpll_recalc_rate()
93 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_determine_rate() local
98 mpll->flags); in mpll_determine_rate()
113 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_set_rate() local
117 params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags); in mpll_set_rate()
119 if (mpll->lock) in mpll_set_rate()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmstar,msc313-mpll.yaml4 $id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
7 title: MStar/Sigmastar MSC313 MPLL
13 The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
20 const: mstar,msc313-mpll
41 mpll@206000 {
42 compatible = "mstar,msc313-mpll";
H A Dmstar,msc313-cpupll.yaml39 #include <dt-bindings/clock/mstar-msc313-mpll.h>
44 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c72 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock() local
78 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
112 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
187 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_get_clock_info() local
219 if (mpll->reference_div < 2) in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
234 mpll->reference_freq = 1432; in radeon_get_clock_info()
239 mpll->reference_freq = 2700; in radeon_get_clock_info()
[all …]
/openbmc/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-v7.dtsi9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
153 mpll: mpll@206000 { label
154 compatible = "mstar,msc313-mpll";
164 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c30 /* MPLL */
31 FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
32 FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
33 FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
34 FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
35 FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
103 "mpll" };
H A Dclk-mt7981-topckgen.c24 FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
25 FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
26 FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
27 FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
28 FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
29 FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
30 FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c356 MPLL, enumerator
412 (selectplls[MPLL] << CPM_CPCCR_SEL_H0PLL_BIT) | in cpu_mux_select()
413 (selectplls[MPLL] << CPM_CPCCR_SEL_H2PLL_BIT); in cpu_mux_select()
455 { CPM_MSCCDR, MPLL, 30 }, in pll_init()
458 { CPM_GPUCDR, MPLL, 30 }, in pll_init()
461 { CPM_BCHCDR, MPLL, 30 }, in pll_init()
473 pll_init_one(MPLL, JZ4780_MPLL_M, JZ4780_MPLL_N, JZ4780_MPLL_OD); in pll_init()
477 cpu_mux_select(MPLL); in pll_init()
478 ddr_mux_select(MPLL); in pll_init()
/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c36 case MPLL: in s5pc100_get_pll_clk()
87 case MPLL: in s5pc110_get_pll_clk()
107 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()
206 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); in get_pclkd1()
236 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atomfirmware.c675 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atomfirmware_get_clock_info() local
734 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
736 mpll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
737 mpll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
738 mpll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
739 mpll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
740 mpll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
741 mpll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
742 mpll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
743 mpll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
H A Damdgpu_atombios.c571 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atombios_get_clock_info() local
643 mpll->reference_freq = in amdgpu_atombios_get_clock_info()
645 mpll->reference_div = 0; in amdgpu_atombios_get_clock_info()
647 mpll->pll_out_min = in amdgpu_atombios_get_clock_info()
649 mpll->pll_out_max = in amdgpu_atombios_get_clock_info()
653 if (mpll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
654 mpll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
656 mpll->pll_in_min = in amdgpu_atombios_get_clock_info()
658 mpll->pll_in_max = in amdgpu_atombios_get_clock_info()
666 mpll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c125 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()
195 case MPLL: in exynos4_get_pll_clk()
225 case MPLL: in exynos4x12_get_pll_clk()
256 case MPLL: in exynos5_get_pll_clk()
277 /* According to the user manual, in EVT1 MPLL and BPLL always gives in exynos5_get_pll_clk()
278 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ in exynos5_get_pll_clk()
279 if (pllreg == MPLL || pllreg == BPLL) { in exynos5_get_pll_clk()
283 case MPLL: in exynos5_get_pll_clk()
314 case MPLL: in exynos542x_get_pll_clk()
437 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-ipq806x-usb.c62 /* Override value for mpll */
105 /* MPLL bits */
125 u32 mpll; member
406 data |= SSPHY_MPLL(phy_dwc3->mpll); in qcom_ipq806x_usb_ss_phy_init()
532 if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll)) in qcom_ipq806x_usb_phy_probe()
533 phy_dwc3->mpll = SSPHY_MPLL_VALUE; in qcom_ipq806x_usb_phy_probe()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c288 bool mpll = Preg == 0x4020; in setPLL_double_lowregs() local
291 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | in setPLL_double_lowregs()
306 if (mpll) { in setPLL_double_lowregs()
322 Pval |= mpll ? 1 << 12 : 1 << 8; in setPLL_double_lowregs()
326 if (mpll) { in setPLL_double_lowregs()
340 if (mpll) { in setPLL_double_lowregs()
349 if (mpll) { in setPLL_double_lowregs()
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq8064-v2.0.dtsi62 qcom,mpll = <5>;
68 qcom,mpll = <5>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx35.c64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
116 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); in _mx35_clocks_init()
H A Dclk-imx27.c34 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
39 "ckih_gate", "mpll", "spll", "cpu_div",
46 static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
63 clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); in _mx27_clocks_init()
66 clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); in _mx27_clocks_init()
H A Dclk-imx31.c33 static const char *mcu_main_sel[] = { "spll", "mpll", };
39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,ipq806x-usb-phy-ss.yaml49 qcom,mpll:
51 description: Override value for mpll.
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c108 * CMU_CPU clocks src to MPLL in board_clock_init()
191 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) in board_clock_init()
210 /* Set MPLL to 800MHz */ in board_clock_init()
281 * Set CLK_SRC_PERIL0 clocks src to MPLL in board_clock_init()
313 * For MOUTmmc0-3 = 800 MHz (MPLL) in board_clock_init()
333 * For MOUTmmc0-3 = 800 MHz (MPLL) in board_clock_init()
352 * For MOUTmmc4 = 800 MHz (MPLL) in board_clock_init()
/openbmc/linux/drivers/clk/mvebu/
H A Dmv98dx3236.c24 * SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
33 * SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
94 { .id = MV98DX3236_CPU_TO_MPLL, .name = "mpll" },
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c191 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
210 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
217 "mpll/2", "spll/4", "mpll/3", "spll/3",
218 "spll/4", "spll/8", "mpll/4", "mpll/8"),
225 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi91 mpll: mpll { label
92 compatible = "sprd,sc9863a-mpll";

123456