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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,mpfs-clkcfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire Clock Control Module
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
17 user nodes by the CLKCFG node phandle and the clock index in the group, from
22 const: microchip,mpfs-clkcfg
26 - description: |
[all …]
H A Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
10 - Conor Dooley <conor.dooley@microchip.com>
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
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/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
11 compatible = "microchip,mpfs";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
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H A Dmpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-icicle-kit-fabric.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
11 /* Clock frequency (in Hz) of the rtcclk */
15 model = "Microchip PolarFire-SoC Icicle Kit";
16 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
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H A Dmpfs-icicle-kit-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
6 "microchip,mpfs";
9 compatible = "microchip,corepwm-rtl-v4";
11 microchip,sync-update-mask = /bits/ 32 <0>;
12 #pwm-cells = <3>;
18 compatible = "microchip,corei2c-rtl-v7";
20 #address-cells = <1>;
21 #size-cells = <0>;
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H A Dmpfs-polarberry.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-polarberry-fabric.dtsi"
9 /* Clock frequency (in Hz) of the rtcclk */
14 compatible = "sundance,polarberry", "microchip,mpfs";
22 stdout-path = "serial0:115200n8";
26 timebase-frequency = <MTIMER_FREQ>;
45 phy-mode = "sgmii";
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H A Dmpfs-sev-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-sev-kit-fabric.dtsi"
9 /* Clock frequency (in Hz) of the rtcclk */
13 #address-cells = <2>;
14 #size-cells = <2>;
15 model = "Microchip PolarFire-SoC SEV Kit";
16 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
28 stdout-path = "serial1:115200n8";
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H A Dmpfs-tysom-m.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2020-2022 - Aldec
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
9 /dts-v1/;
11 #include "mpfs.dtsi"
12 #include "mpfs-tysom-m-fabric.dtsi"
14 /* Clock frequency (in Hz) of the rtcclk */
18 model = "Aldec TySOM-M-MPFS250T-REV2";
19 compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
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H A Dmpfs-m100pfsevp.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
8 /dts-v1/;
10 #include "mpfs.dtsi"
11 #include "mpfs-m100pfs-fabric.dtsi"
13 /* Clock frequency (in Hz) of the rtcclk */
18 compatible = "aries,m100pfsevp", "microchip,mpfs";
33 stdout-path = "serial1:115200n8";
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Conor Dooley <conor.dooley@microchip.com>
17 - $ref: spi-controller.yaml#
22 - items:
23 - const: microchip,mpfs-qspi
24 - const: microchip,coreqspi-rtl-v2
25 - const: microchip,coreqspi-rtl-v2 # FPGA QSPI
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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dmicrochip,mfps-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
14 - Daire McNamara <daire.mcnamara@microchip.com>
15 - Lewis Hanly <lewis.hanly@microchip.com>
20 - microchip,mpfs-rtc
27 - description: |
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dmicrochip,mpfs-musb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MPFS USB Controller
10 - $ref: usb-drd.yaml#
13 - Conor Dooley <conor.dooley@microchip.com>
18 - microchip,mpfs-musb
29 interrupt-names:
31 - const: dma
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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dmicrochip,corei2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MPFS I2C Controller
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
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/openbmc/linux/drivers/reset/
H A Dreset-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
14 #include <linux/reset-controller.h>
15 #include <dt-bindings/clock/microchip,mpfs-clock.h>
16 #include <soc/microchip/mpfs.h>
20 * defines in the dt to make things easier to configure - so this is accounting
32 * Peripheral clock resets
42 reg = mpfs_reset_read(rcdev->dev); in mpfs_assert()
44 mpfs_reset_write(rcdev->dev, reg); in mpfs_assert()
58 reg = mpfs_reset_read(rcdev->dev); in mpfs_deassert()
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/openbmc/linux/drivers/clk/microchip/
H A Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PolarFire SoC MSS/core complex clock control
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/microchip,mpfs-clock.h>
14 #include <soc/microchip/mpfs.h>
67 * mpfs clk block while a software locked register is being written.
86 * The only two supported reference clock frequencies for the PolarFire SoC are
99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
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H A Dclk-mpfs-ccc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "asm-generic/errno-base.h"
8 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/microchip,mpfs-clock.h>
76 void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset; in mpfs_ccc_pll_recalc_rate()
77 void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR; in mpfs_ccc_pll_recalc_rate()
91 void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR; in mpfs_ccc_pll_get_parent()
167 char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i); in mpfs_ccc_register_outputs()
170 return -ENOMEM; in mpfs_ccc_register_outputs()
172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0); in mpfs_ccc_register_outputs()
[all …]
/openbmc/linux/drivers/usb/musb/
H A Dmpfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * PolarFire SoC (MPFS) MUSB Glue Layer
5 * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
11 #include <linux/dma-mapping.h>
58 spin_lock_irqsave(&musb->lock, flags); in mpfs_musb_interrupt()
60 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); in mpfs_musb_interrupt()
61 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); in mpfs_musb_interrupt()
62 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); in mpfs_musb_interrupt()
64 if (musb->int_usb || musb->int_tx || musb->int_rx) { in mpfs_musb_interrupt()
65 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); in mpfs_musb_interrupt()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
36 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-mpfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip MPFS RTC driver
5 * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
65 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
68 writel(ctrl, rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
73 u32 val = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
77 writel(val, rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
83 (void)readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
91 time = readl(rtcdev->base + DATETIME_LOWER_REG); in mpfs_rtc_readtime()
92 time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32; in mpfs_rtc_readtime()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "Real Time Clock"
29 If you say yes here, the system time (wall clock) will be set using
39 clock, usually rtc0. Initialization is done when the system
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
46 system will need an external clock source (like an NTP server).
48 If the clock you specify here is not battery backed, it may still
57 If you say yes here, the system time (wall clock) will be stored
112 Say yes here if you want to use your system clock RTC through
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-microchip-core.c1 // SPDX-License-Identifier: (GPL-2.0)
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
108 u32 clk_gen; /* divider for spi output clock generated by the controller */
119 return readl(spi->regs + reg); in mchp_corespi_read()
124 writel(val, spi->regs + reg); in mchp_corespi_write()
141 fifo_max = min(spi->rx_len, FIFO_DEPTH); in mchp_corespi_read_fifo()
146 if (spi->rx_buf) in mchp_corespi_read_fifo()
147 *spi->rx_buf++ = data; in mchp_corespi_read_fifo()
150 spi->rx_len -= i; in mchp_corespi_read_fifo()
151 spi->pending -= i; in mchp_corespi_read_fifo()
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 subdir-ccflags-y += -I$(src)
9 obj-$(CONFIG_MLX5_CORE) += mlx5_core.o
14 mlx5_core-y := main.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \
25 mlx5_core-$(CONFIG_MLX5_CORE_EN) += en/rqt.o en/tir.o en/rss.o en/rx_res.o \
37 mlx5_core-$(CONFIG_MLX5_EN_ARFS) += en_arfs.o
38 mlx5_core-$(CONFIG_MLX5_EN_RXNFC) += en_fs_ethtool.o
39 mlx5_core-$(CONFIG_MLX5_CORE_EN_DCB) += en_dcbnl.o en/port_buffer.o
40 mlx5_core-$(CONFIG_PCI_HYPERV_INTERFACE) += en/hv_vhca_stats.o
41 mlx5_core-$(CONFIG_MLX5_ESWITCH) += lag/mp.o lag/port_sel.o lib/geneve.o lib/port_tun.o \
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-microchip-corei2c.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018-2022 Microchip Corporation. All rights reserved.
91 * struct mchp_corei2c_dev - Microchip CoreI2C device private data
95 * @i2c_clk: clock reference for i2c input clock
101 * @bus_clk_rate: current i2c bus clock rate
129 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_disable()
132 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_disable()
137 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_enable()
140 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_enable()
151 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_stop()
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/openbmc/linux/include/linux/mlx5/
H A Ddriver.h2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
220 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
378 #define MLX5_24BIT_MASK ((1 << 24) - 1)
618 struct mlx5_mpfs *mpfs; member
801 struct mlx5_clock clock; member
904 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
910 return ioread32be(&dev->iseg->fw_rev) & 0xffff; in fw_rev_maj()
915 return ioread32be(&dev->iseg->fw_rev) >> 16; in fw_rev_min()
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