1635e5e73SDaire McNamara // SPDX-License-Identifier: GPL-2.0-only
2635e5e73SDaire McNamara /*
3d325268bSConor Dooley * PolarFire SoC MSS/core complex clock control
4d325268bSConor Dooley *
5d325268bSConor Dooley * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
6635e5e73SDaire McNamara */
7b56bae2dSConor Dooley #include <linux/auxiliary_bus.h>
8635e5e73SDaire McNamara #include <linux/clk-provider.h>
9635e5e73SDaire McNamara #include <linux/io.h>
10635e5e73SDaire McNamara #include <linux/module.h>
11635e5e73SDaire McNamara #include <linux/platform_device.h>
12635e5e73SDaire McNamara #include <linux/slab.h>
13635e5e73SDaire McNamara #include <dt-bindings/clock/microchip,mpfs-clock.h>
14b56bae2dSConor Dooley #include <soc/microchip/mpfs.h>
15635e5e73SDaire McNamara
16635e5e73SDaire McNamara /* address offset of control registers */
17445c2da8SConor Dooley #define REG_MSSPLL_REF_CR 0x08u
18445c2da8SConor Dooley #define REG_MSSPLL_POSTDIV_CR 0x10u
19445c2da8SConor Dooley #define REG_MSSPLL_SSCG_2_CR 0x2Cu
20635e5e73SDaire McNamara #define REG_CLOCK_CONFIG_CR 0x08u
211c6a7ea3SConor Dooley #define REG_RTC_CLOCK_CR 0x0Cu
22635e5e73SDaire McNamara #define REG_SUBBLK_CLOCK_CR 0x84u
23635e5e73SDaire McNamara #define REG_SUBBLK_RESET_CR 0x88u
24635e5e73SDaire McNamara
25445c2da8SConor Dooley #define MSSPLL_FBDIV_SHIFT 0x00u
26445c2da8SConor Dooley #define MSSPLL_FBDIV_WIDTH 0x0Cu
27445c2da8SConor Dooley #define MSSPLL_REFDIV_SHIFT 0x08u
28445c2da8SConor Dooley #define MSSPLL_REFDIV_WIDTH 0x06u
29445c2da8SConor Dooley #define MSSPLL_POSTDIV_SHIFT 0x08u
30445c2da8SConor Dooley #define MSSPLL_POSTDIV_WIDTH 0x07u
31445c2da8SConor Dooley #define MSSPLL_FIXED_DIV 4u
32445c2da8SConor Dooley
33635e5e73SDaire McNamara struct mpfs_clock_data {
34b56bae2dSConor Dooley struct device *dev;
35635e5e73SDaire McNamara void __iomem *base;
36445c2da8SConor Dooley void __iomem *msspll_base;
37635e5e73SDaire McNamara struct clk_hw_onecell_data hw_data;
38635e5e73SDaire McNamara };
39635e5e73SDaire McNamara
40445c2da8SConor Dooley struct mpfs_msspll_hw_clock {
41445c2da8SConor Dooley void __iomem *base;
42445c2da8SConor Dooley unsigned int id;
43445c2da8SConor Dooley u32 reg_offset;
44445c2da8SConor Dooley u32 shift;
45445c2da8SConor Dooley u32 width;
46445c2da8SConor Dooley u32 flags;
47445c2da8SConor Dooley struct clk_hw hw;
48445c2da8SConor Dooley struct clk_init_data init;
49445c2da8SConor Dooley };
50445c2da8SConor Dooley
51445c2da8SConor Dooley #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
52445c2da8SConor Dooley
53635e5e73SDaire McNamara struct mpfs_cfg_hw_clock {
544da2404bSConor Dooley struct clk_divider cfg;
55635e5e73SDaire McNamara struct clk_init_data init;
5652fe6b52SConor Dooley unsigned int id;
5752fe6b52SConor Dooley u32 reg_offset;
58635e5e73SDaire McNamara };
59635e5e73SDaire McNamara
60635e5e73SDaire McNamara struct mpfs_periph_hw_clock {
61d8155697SConor Dooley struct clk_gate periph;
6252fe6b52SConor Dooley unsigned int id;
63635e5e73SDaire McNamara };
64635e5e73SDaire McNamara
65635e5e73SDaire McNamara /*
66635e5e73SDaire McNamara * mpfs_clk_lock prevents anything else from writing to the
67635e5e73SDaire McNamara * mpfs clk block while a software locked register is being written.
68635e5e73SDaire McNamara */
69635e5e73SDaire McNamara static DEFINE_SPINLOCK(mpfs_clk_lock);
70635e5e73SDaire McNamara
71445c2da8SConor Dooley static const struct clk_parent_data mpfs_ext_ref[] = {
72635e5e73SDaire McNamara { .index = 0 },
73635e5e73SDaire McNamara };
74635e5e73SDaire McNamara
75635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_cpu_axi_table[] = {
76635e5e73SDaire McNamara { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
77635e5e73SDaire McNamara { 0, 0 }
78635e5e73SDaire McNamara };
79635e5e73SDaire McNamara
80635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_ahb_table[] = {
81635e5e73SDaire McNamara { 1, 2 }, { 2, 4}, { 3, 8 },
82635e5e73SDaire McNamara { 0, 0 }
83635e5e73SDaire McNamara };
84635e5e73SDaire McNamara
851c6a7ea3SConor Dooley /*
861c6a7ea3SConor Dooley * The only two supported reference clock frequencies for the PolarFire SoC are
871c6a7ea3SConor Dooley * 100 and 125 MHz, as the rtc reference is required to be 1 MHz.
881c6a7ea3SConor Dooley * It therefore only needs to have divider table entries corresponding to
891c6a7ea3SConor Dooley * divide by 100 and 125.
901c6a7ea3SConor Dooley */
911c6a7ea3SConor Dooley static const struct clk_div_table mpfs_div_rtcref_table[] = {
921c6a7ea3SConor Dooley { 100, 100 }, { 125, 125 },
931c6a7ea3SConor Dooley { 0, 0 }
941c6a7ea3SConor Dooley };
951c6a7ea3SConor Dooley
mpfs_clk_msspll_recalc_rate(struct clk_hw * hw,unsigned long prate)96445c2da8SConor Dooley static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate)
97445c2da8SConor Dooley {
98445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
99445c2da8SConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
100445c2da8SConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
101445c2da8SConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
102445c2da8SConor Dooley u32 mult, ref_div, postdiv;
103445c2da8SConor Dooley
104445c2da8SConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
105445c2da8SConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
106445c2da8SConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
107445c2da8SConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
108445c2da8SConor Dooley postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
109445c2da8SConor Dooley postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
110445c2da8SConor Dooley
111445c2da8SConor Dooley return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv);
112445c2da8SConor Dooley }
113445c2da8SConor Dooley
mpfs_clk_msspll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)11414016e4aSConor Dooley static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
11514016e4aSConor Dooley {
11614016e4aSConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
11714016e4aSConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
11814016e4aSConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
11914016e4aSConor Dooley u32 mult, ref_div;
12014016e4aSConor Dooley unsigned long rate_before_ctrl;
12114016e4aSConor Dooley
12214016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
12314016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
12414016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
12514016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
12614016e4aSConor Dooley
12714016e4aSConor Dooley rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
12814016e4aSConor Dooley
12914016e4aSConor Dooley return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
13014016e4aSConor Dooley msspll_hw->flags);
13114016e4aSConor Dooley }
13214016e4aSConor Dooley
mpfs_clk_msspll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)13314016e4aSConor Dooley static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
13414016e4aSConor Dooley {
13514016e4aSConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
13614016e4aSConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
13714016e4aSConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
13814016e4aSConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
13914016e4aSConor Dooley u32 mult, ref_div, postdiv;
14014016e4aSConor Dooley int divider_setting;
14114016e4aSConor Dooley unsigned long rate_before_ctrl, flags;
14214016e4aSConor Dooley
14314016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
14414016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
14514016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
14614016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
14714016e4aSConor Dooley
14814016e4aSConor Dooley rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
14914016e4aSConor Dooley divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
15014016e4aSConor Dooley msspll_hw->flags);
15114016e4aSConor Dooley
15214016e4aSConor Dooley if (divider_setting < 0)
15314016e4aSConor Dooley return divider_setting;
15414016e4aSConor Dooley
15514016e4aSConor Dooley spin_lock_irqsave(&mpfs_clk_lock, flags);
15614016e4aSConor Dooley
15714016e4aSConor Dooley postdiv = readl_relaxed(postdiv_addr);
15814016e4aSConor Dooley postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT);
15914016e4aSConor Dooley writel_relaxed(postdiv, postdiv_addr);
16014016e4aSConor Dooley
16114016e4aSConor Dooley spin_unlock_irqrestore(&mpfs_clk_lock, flags);
16214016e4aSConor Dooley
16314016e4aSConor Dooley return 0;
16414016e4aSConor Dooley }
16514016e4aSConor Dooley
166445c2da8SConor Dooley static const struct clk_ops mpfs_clk_msspll_ops = {
167445c2da8SConor Dooley .recalc_rate = mpfs_clk_msspll_recalc_rate,
16814016e4aSConor Dooley .round_rate = mpfs_clk_msspll_round_rate,
16914016e4aSConor Dooley .set_rate = mpfs_clk_msspll_set_rate,
170445c2da8SConor Dooley };
171445c2da8SConor Dooley
172445c2da8SConor Dooley #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \
173445c2da8SConor Dooley .id = _id, \
174445c2da8SConor Dooley .shift = _shift, \
175445c2da8SConor Dooley .width = _width, \
176445c2da8SConor Dooley .reg_offset = _offset, \
177445c2da8SConor Dooley .flags = _flags, \
178445c2da8SConor Dooley .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \
179445c2da8SConor Dooley }
180445c2da8SConor Dooley
181445c2da8SConor Dooley static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
182445c2da8SConor Dooley CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,
183445c2da8SConor Dooley MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR),
184445c2da8SConor Dooley };
185445c2da8SConor Dooley
mpfs_clk_register_mssplls(struct device * dev,struct mpfs_msspll_hw_clock * msspll_hws,unsigned int num_clks,struct mpfs_clock_data * data)186445c2da8SConor Dooley static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
187445c2da8SConor Dooley unsigned int num_clks, struct mpfs_clock_data *data)
188445c2da8SConor Dooley {
189445c2da8SConor Dooley unsigned int i;
190445c2da8SConor Dooley int ret;
191445c2da8SConor Dooley
192445c2da8SConor Dooley for (i = 0; i < num_clks; i++) {
193445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
194445c2da8SConor Dooley
195e7df7ba0SConor Dooley msspll_hw->base = data->msspll_base;
196e7df7ba0SConor Dooley ret = devm_clk_hw_register(dev, &msspll_hw->hw);
197445c2da8SConor Dooley if (ret)
198445c2da8SConor Dooley return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
199445c2da8SConor Dooley CLK_MSSPLL);
200445c2da8SConor Dooley
201445c2da8SConor Dooley data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;
202445c2da8SConor Dooley }
203445c2da8SConor Dooley
204445c2da8SConor Dooley return 0;
205445c2da8SConor Dooley }
206445c2da8SConor Dooley
207445c2da8SConor Dooley /*
208445c2da8SConor Dooley * "CFG" clocks
209445c2da8SConor Dooley */
210445c2da8SConor Dooley
211445c2da8SConor Dooley #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
21252fe6b52SConor Dooley .id = _id, \
213635e5e73SDaire McNamara .cfg.shift = _shift, \
214635e5e73SDaire McNamara .cfg.width = _width, \
215635e5e73SDaire McNamara .cfg.table = _table, \
21652fe6b52SConor Dooley .reg_offset = _offset, \
217445c2da8SConor Dooley .cfg.flags = _flags, \
2184da2404bSConor Dooley .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
2194da2404bSConor Dooley .cfg.lock = &mpfs_clk_lock, \
220635e5e73SDaire McNamara }
221635e5e73SDaire McNamara
2225da39ac5SConor Dooley #define CLK_CPU_OFFSET 0u
2235da39ac5SConor Dooley #define CLK_AXI_OFFSET 1u
2245da39ac5SConor Dooley #define CLK_AHB_OFFSET 2u
2255da39ac5SConor Dooley #define CLK_RTCREF_OFFSET 3u
2265da39ac5SConor Dooley
227635e5e73SDaire McNamara static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
228445c2da8SConor Dooley CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0,
229445c2da8SConor Dooley REG_CLOCK_CONFIG_CR),
230445c2da8SConor Dooley CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0,
231445c2da8SConor Dooley REG_CLOCK_CONFIG_CR),
232445c2da8SConor Dooley CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0,
233445c2da8SConor Dooley REG_CLOCK_CONFIG_CR),
2341c6a7ea3SConor Dooley {
23552fe6b52SConor Dooley .id = CLK_RTCREF,
2361c6a7ea3SConor Dooley .cfg.shift = 0,
2371c6a7ea3SConor Dooley .cfg.width = 12,
2381c6a7ea3SConor Dooley .cfg.table = mpfs_div_rtcref_table,
23952fe6b52SConor Dooley .reg_offset = REG_RTC_CLOCK_CR,
2401c6a7ea3SConor Dooley .cfg.flags = CLK_DIVIDER_ONE_BASED,
2414da2404bSConor Dooley .cfg.hw.init =
2424da2404bSConor Dooley CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
2431c6a7ea3SConor Dooley }
244635e5e73SDaire McNamara };
245635e5e73SDaire McNamara
mpfs_clk_register_cfgs(struct device * dev,struct mpfs_cfg_hw_clock * cfg_hws,unsigned int num_clks,struct mpfs_clock_data * data)246635e5e73SDaire McNamara static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
247635e5e73SDaire McNamara unsigned int num_clks, struct mpfs_clock_data *data)
248635e5e73SDaire McNamara {
249635e5e73SDaire McNamara unsigned int i, id;
250635e5e73SDaire McNamara int ret;
251635e5e73SDaire McNamara
252635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) {
253635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
254635e5e73SDaire McNamara
255e7df7ba0SConor Dooley cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
2564da2404bSConor Dooley ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
257635e5e73SDaire McNamara if (ret)
258635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
25952fe6b52SConor Dooley cfg_hw->id);
260635e5e73SDaire McNamara
26152fe6b52SConor Dooley id = cfg_hw->id;
2624da2404bSConor Dooley data->hw_data.hws[id] = &cfg_hw->cfg.hw;
263635e5e73SDaire McNamara }
264635e5e73SDaire McNamara
265635e5e73SDaire McNamara return 0;
266635e5e73SDaire McNamara }
267635e5e73SDaire McNamara
268445c2da8SConor Dooley /*
269445c2da8SConor Dooley * peripheral clocks - devices connected to axi or ahb buses.
270445c2da8SConor Dooley */
271445c2da8SConor Dooley
272635e5e73SDaire McNamara #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
27352fe6b52SConor Dooley .id = _id, \
274d8155697SConor Dooley .periph.bit_idx = _shift, \
275d8155697SConor Dooley .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
276635e5e73SDaire McNamara _flags), \
277d8155697SConor Dooley .periph.lock = &mpfs_clk_lock, \
278635e5e73SDaire McNamara }
279635e5e73SDaire McNamara
2804da2404bSConor Dooley #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
281635e5e73SDaire McNamara
282635e5e73SDaire McNamara /*
283635e5e73SDaire McNamara * Critical clocks:
284635e5e73SDaire McNamara * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
285635e5e73SDaire McNamara * trap handler
286635e5e73SDaire McNamara * - CLK_MMUART0: reserved by the hss
287635e5e73SDaire McNamara * - CLK_DDRC: provides clock to the ddr subsystem
28805d27090SConor Dooley * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
28905d27090SConor Dooley * if the AHB interface clock is disabled
290a2438f82SConor Dooley * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
291a2438f82SConor Dooley * clock domain crossers which provide the interface to the FPGA fabric. Disabling them
292a2438f82SConor Dooley * causes the FPGA fabric to go into reset.
293a2438f82SConor Dooley * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
294635e5e73SDaire McNamara */
295635e5e73SDaire McNamara
296635e5e73SDaire McNamara static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
297635e5e73SDaire McNamara CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
298635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
299635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
300635e5e73SDaire McNamara CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
3011c6a7ea3SConor Dooley CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0),
302635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
303635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
304635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
305635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0),
306635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0),
307635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0),
308635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0),
309635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0),
310635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0),
311635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0),
312635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0),
313635e5e73SDaire McNamara CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0),
31405d27090SConor Dooley CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
315635e5e73SDaire McNamara CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0),
316635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0),
317635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),
318635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0),
319635e5e73SDaire McNamara CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
3208f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL),
3218f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL),
3228f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL),
3238f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL),
324a2438f82SConor Dooley CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL),
325635e5e73SDaire McNamara CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
326635e5e73SDaire McNamara };
327635e5e73SDaire McNamara
mpfs_clk_register_periphs(struct device * dev,struct mpfs_periph_hw_clock * periph_hws,int num_clks,struct mpfs_clock_data * data)328635e5e73SDaire McNamara static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
329635e5e73SDaire McNamara int num_clks, struct mpfs_clock_data *data)
330635e5e73SDaire McNamara {
331635e5e73SDaire McNamara unsigned int i, id;
332635e5e73SDaire McNamara int ret;
333635e5e73SDaire McNamara
334635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) {
335635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
336635e5e73SDaire McNamara
337e7df7ba0SConor Dooley periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
338d8155697SConor Dooley ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
339635e5e73SDaire McNamara if (ret)
340635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
34152fe6b52SConor Dooley periph_hw->id);
342635e5e73SDaire McNamara
34352fe6b52SConor Dooley id = periph_hws[i].id;
344d8155697SConor Dooley data->hw_data.hws[id] = &periph_hw->periph.hw;
345635e5e73SDaire McNamara }
346635e5e73SDaire McNamara
347635e5e73SDaire McNamara return 0;
348635e5e73SDaire McNamara }
349635e5e73SDaire McNamara
350b56bae2dSConor Dooley /*
351b56bae2dSConor Dooley * Peripheral clock resets
352b56bae2dSConor Dooley */
353b56bae2dSConor Dooley
354b56bae2dSConor Dooley #if IS_ENABLED(CONFIG_RESET_CONTROLLER)
355b56bae2dSConor Dooley
mpfs_reset_read(struct device * dev)356b56bae2dSConor Dooley u32 mpfs_reset_read(struct device *dev)
357b56bae2dSConor Dooley {
358b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
359b56bae2dSConor Dooley
360b56bae2dSConor Dooley return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR);
361b56bae2dSConor Dooley }
362b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS);
363b56bae2dSConor Dooley
mpfs_reset_write(struct device * dev,u32 val)364b56bae2dSConor Dooley void mpfs_reset_write(struct device *dev, u32 val)
365b56bae2dSConor Dooley {
366b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
367b56bae2dSConor Dooley
368b56bae2dSConor Dooley writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR);
369b56bae2dSConor Dooley }
370b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS);
371b56bae2dSConor Dooley
mpfs_reset_unregister_adev(void * _adev)372b56bae2dSConor Dooley static void mpfs_reset_unregister_adev(void *_adev)
373b56bae2dSConor Dooley {
374b56bae2dSConor Dooley struct auxiliary_device *adev = _adev;
375b56bae2dSConor Dooley
376b56bae2dSConor Dooley auxiliary_device_delete(adev);
377*7455b700SConor Dooley auxiliary_device_uninit(adev);
378b56bae2dSConor Dooley }
379b56bae2dSConor Dooley
mpfs_reset_adev_release(struct device * dev)380b56bae2dSConor Dooley static void mpfs_reset_adev_release(struct device *dev)
381b56bae2dSConor Dooley {
382b56bae2dSConor Dooley struct auxiliary_device *adev = to_auxiliary_dev(dev);
383b56bae2dSConor Dooley
384b56bae2dSConor Dooley kfree(adev);
385b56bae2dSConor Dooley }
386b56bae2dSConor Dooley
mpfs_reset_adev_alloc(struct mpfs_clock_data * clk_data)387b56bae2dSConor Dooley static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data)
388b56bae2dSConor Dooley {
389b56bae2dSConor Dooley struct auxiliary_device *adev;
390b56bae2dSConor Dooley int ret;
391b56bae2dSConor Dooley
392b56bae2dSConor Dooley adev = kzalloc(sizeof(*adev), GFP_KERNEL);
393b56bae2dSConor Dooley if (!adev)
394b56bae2dSConor Dooley return ERR_PTR(-ENOMEM);
395b56bae2dSConor Dooley
396b56bae2dSConor Dooley adev->name = "reset-mpfs";
397b56bae2dSConor Dooley adev->dev.parent = clk_data->dev;
398b56bae2dSConor Dooley adev->dev.release = mpfs_reset_adev_release;
399b56bae2dSConor Dooley adev->id = 666u;
400b56bae2dSConor Dooley
401b56bae2dSConor Dooley ret = auxiliary_device_init(adev);
402b56bae2dSConor Dooley if (ret) {
403b56bae2dSConor Dooley kfree(adev);
404b56bae2dSConor Dooley return ERR_PTR(ret);
405b56bae2dSConor Dooley }
406b56bae2dSConor Dooley
407b56bae2dSConor Dooley return adev;
408b56bae2dSConor Dooley }
409b56bae2dSConor Dooley
mpfs_reset_controller_register(struct mpfs_clock_data * clk_data)410b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
411b56bae2dSConor Dooley {
412b56bae2dSConor Dooley struct auxiliary_device *adev;
413b56bae2dSConor Dooley int ret;
414b56bae2dSConor Dooley
415b56bae2dSConor Dooley adev = mpfs_reset_adev_alloc(clk_data);
416b56bae2dSConor Dooley if (IS_ERR(adev))
417b56bae2dSConor Dooley return PTR_ERR(adev);
418b56bae2dSConor Dooley
419b56bae2dSConor Dooley ret = auxiliary_device_add(adev);
420b56bae2dSConor Dooley if (ret) {
421b56bae2dSConor Dooley auxiliary_device_uninit(adev);
422b56bae2dSConor Dooley return ret;
423b56bae2dSConor Dooley }
424b56bae2dSConor Dooley
425b56bae2dSConor Dooley return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev);
426b56bae2dSConor Dooley }
427b56bae2dSConor Dooley
428b56bae2dSConor Dooley #else /* !CONFIG_RESET_CONTROLLER */
429b56bae2dSConor Dooley
mpfs_reset_controller_register(struct mpfs_clock_data * clk_data)430b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
431b56bae2dSConor Dooley {
432b56bae2dSConor Dooley return 0;
433b56bae2dSConor Dooley }
434b56bae2dSConor Dooley
435b56bae2dSConor Dooley #endif /* !CONFIG_RESET_CONTROLLER */
436b56bae2dSConor Dooley
mpfs_clk_probe(struct platform_device * pdev)437635e5e73SDaire McNamara static int mpfs_clk_probe(struct platform_device *pdev)
438635e5e73SDaire McNamara {
439635e5e73SDaire McNamara struct device *dev = &pdev->dev;
440635e5e73SDaire McNamara struct mpfs_clock_data *clk_data;
441635e5e73SDaire McNamara unsigned int num_clks;
442635e5e73SDaire McNamara int ret;
443635e5e73SDaire McNamara
444445c2da8SConor Dooley /* CLK_RESERVED is not part of clock arrays, so add 1 */
445445c2da8SConor Dooley num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks)
446445c2da8SConor Dooley + ARRAY_SIZE(mpfs_periph_clks) + 1;
447635e5e73SDaire McNamara
448635e5e73SDaire McNamara clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL);
449635e5e73SDaire McNamara if (!clk_data)
450635e5e73SDaire McNamara return -ENOMEM;
451635e5e73SDaire McNamara
452635e5e73SDaire McNamara clk_data->base = devm_platform_ioremap_resource(pdev, 0);
453635e5e73SDaire McNamara if (IS_ERR(clk_data->base))
454635e5e73SDaire McNamara return PTR_ERR(clk_data->base);
455635e5e73SDaire McNamara
456445c2da8SConor Dooley clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
457445c2da8SConor Dooley if (IS_ERR(clk_data->msspll_base))
458445c2da8SConor Dooley return PTR_ERR(clk_data->msspll_base);
459445c2da8SConor Dooley
460635e5e73SDaire McNamara clk_data->hw_data.num = num_clks;
461b56bae2dSConor Dooley clk_data->dev = dev;
462b56bae2dSConor Dooley dev_set_drvdata(dev, clk_data);
463635e5e73SDaire McNamara
464445c2da8SConor Dooley ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks),
465445c2da8SConor Dooley clk_data);
466445c2da8SConor Dooley if (ret)
467445c2da8SConor Dooley return ret;
468445c2da8SConor Dooley
469635e5e73SDaire McNamara ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data);
470635e5e73SDaire McNamara if (ret)
471635e5e73SDaire McNamara return ret;
472635e5e73SDaire McNamara
473635e5e73SDaire McNamara ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks),
474635e5e73SDaire McNamara clk_data);
475635e5e73SDaire McNamara if (ret)
476635e5e73SDaire McNamara return ret;
477635e5e73SDaire McNamara
478635e5e73SDaire McNamara ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
479635e5e73SDaire McNamara if (ret)
480635e5e73SDaire McNamara return ret;
481635e5e73SDaire McNamara
482b56bae2dSConor Dooley return mpfs_reset_controller_register(clk_data);
483635e5e73SDaire McNamara }
484635e5e73SDaire McNamara
485635e5e73SDaire McNamara static const struct of_device_id mpfs_clk_of_match_table[] = {
486635e5e73SDaire McNamara { .compatible = "microchip,mpfs-clkcfg", },
487635e5e73SDaire McNamara {}
488635e5e73SDaire McNamara };
489b56bae2dSConor Dooley MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table);
490635e5e73SDaire McNamara
491635e5e73SDaire McNamara static struct platform_driver mpfs_clk_driver = {
492635e5e73SDaire McNamara .probe = mpfs_clk_probe,
493635e5e73SDaire McNamara .driver = {
494635e5e73SDaire McNamara .name = "microchip-mpfs-clkcfg",
495635e5e73SDaire McNamara .of_match_table = mpfs_clk_of_match_table,
496635e5e73SDaire McNamara },
497635e5e73SDaire McNamara };
498635e5e73SDaire McNamara
clk_mpfs_init(void)499635e5e73SDaire McNamara static int __init clk_mpfs_init(void)
500635e5e73SDaire McNamara {
501635e5e73SDaire McNamara return platform_driver_register(&mpfs_clk_driver);
502635e5e73SDaire McNamara }
503635e5e73SDaire McNamara core_initcall(clk_mpfs_init);
504635e5e73SDaire McNamara
clk_mpfs_exit(void)505635e5e73SDaire McNamara static void __exit clk_mpfs_exit(void)
506635e5e73SDaire McNamara {
507635e5e73SDaire McNamara platform_driver_unregister(&mpfs_clk_driver);
508635e5e73SDaire McNamara }
509635e5e73SDaire McNamara module_exit(clk_mpfs_exit);
510635e5e73SDaire McNamara
511635e5e73SDaire McNamara MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
512d325268bSConor Dooley MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>");
513d325268bSConor Dooley MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
514d325268bSConor Dooley MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
515d325268bSConor Dooley