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/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/openbmc/linux/drivers/interconnect/imx/
H A Dimx8mp.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
23 .reg = 0x180,
24 .mode = IMX_NOC_MODE_FIXED,
28 .reg = 0x200,
29 .mode = IMX_NOC_MODE_FIXED,
33 .reg = 0x280,
34 .mode = IMX_NOC_MODE_FIXED,
38 .reg = 0x300,
39 .mode = IMX_NOC_MODE_FIXED,
[all …]
/openbmc/linux/drivers/platform/x86/
H A Dmlx-platform.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
12 #include <linux/i2c-mux.h>
17 #include <linux/platform_data/i2c-mux-reg.h>
297 #define MLXPLAT_CPLD_NR_NONE -1
341 /* mlxplat_priv - platform private data
342 * @pdev_i2c - i2c controller platform device
343 * @pdev_mux - array of mux platform devices
344 * @pdev_hotplug - hotplug platform devices
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
[all …]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
[all …]
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
[all …]
/openbmc/linux/arch/arm/mach-omap1/
H A Dmux.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation
13 * - W8 = ball
14 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
15 * - MMC2_DAT0 = function
21 #include <linux/soc/ti/omap1-mux.h>
23 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
24 #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
27 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ argument
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad5592r.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,ad5592r
16 - adi,ad5593r
18 reg:
21 spi-max-frequency:
24 spi-cpol: true
26 "#address-cells":
[all …]
/openbmc/u-boot/board/freescale/common/
H A Dpfuze.c1 // SPDX-License-Identifier: GPL-2.0+
12 int pfuze_mode_init(struct pmic *p, u32 mode) in pfuze_mode_init() argument
29 return -EINVAL; in pfuze_mode_init()
32 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); in pfuze_mode_init()
34 printf("Set SW1AB mode error!\n"); in pfuze_mode_init()
38 for (i = 0; i < switch_num - 1; i++) { in pfuze_mode_init()
39 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); in pfuze_mode_init()
41 printf("Set switch 0x%x mode error!\n", in pfuze_mode_init()
54 unsigned int reg; in pfuze_common_init() local
65 pmic_reg_read(p, PFUZE100_DEVICEID, &reg); in pfuze_common_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-pcb8290.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
9 /dts-v1/;
11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
15 compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
17 gpio-restart {
18 compatible = "gpio-restart";
29 miim_a_pins: mdio-pins {
35 pps_out_pins: pps-out-pins {
41 ptp_ext_pins: ptp-ext-pins {
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dhi8435.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Holt Integrated Circuits HI-8435 threshold detector driver
24 /* Register offsets for HI-8435 */
50 unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */
51 unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */
55 static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) in hi8435_readb() argument
57 reg |= HI8435_READ_OPCODE; in hi8435_readb()
58 return spi_write_then_read(priv->spi, &reg, 1, val, 1); in hi8435_readb()
61 static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val) in hi8435_readw() argument
66 reg |= HI8435_READ_OPCODE; in hi8435_readw()
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/openbmc/linux/drivers/regulator/
H A Dmcp16502.c1 // SPDX-License-Identifier: GPL-2.0
9 // Inspired from tps65086-regulator.c
30 * Performance, Active, Low-power, Hibernate.
33 * Each regulator has a register for each power mode. To access a register
34 * for a specific regulator and mode BASE_* and OFFSET_* need to be added.
41 * a low-power state while the PMIC is in Active mode. They are supposed to be
42 * configured at startup and then simply transition to/from a global low-power
45 * This driver keeps the PMIC in Active mode, Low-power state is set for the
46 * regulators by enabling/disabling operating mode (FPWM or Auto PFM).
48 * The PMIC's Low-power and Hibernate modes are used during standby/suspend.
[all …]
/openbmc/linux/drivers/staging/ks7010/
H A Dks_wlan_net.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2005-2008 KeyStream Corp.
38 #define MIN_KEY_SIZE 5 /* 40 bits RC4 - WEP */
41 u8 key[16]; /* 40-bit and 104-bit keys */
62 struct iw_statistics *wstats = &priv->wstats; in ks_wlan_update_phy_information()
64 netdev_dbg(priv->net_dev, "in_interrupt = %ld\n", in_interrupt()); in ks_wlan_update_phy_information()
66 if (priv->dev_state < DEVICE_STATE_READY) in ks_wlan_update_phy_information()
67 return -EBUSY; /* not finished initialize */ in ks_wlan_update_phy_information()
70 return -EPERM; in ks_wlan_update_phy_information()
73 wstats->status = priv->reg.operation_mode; /* Operation mode */ in ks_wlan_update_phy_information()
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
24 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
26 return mv88e6xxx_read(chip, addr, reg, val); in mv88e6xxx_port_read()
29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_wait_bit() argument
32 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_wait_bit()
34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); in mv88e6xxx_port_wait_bit()
37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
40 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
156 void __iomem *reg; member
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
213 priv->phy_params = params; in xenon_alloc_emmc_phy()
214 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
215 priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs; in xenon_alloc_emmc_phy()
[all …]
/openbmc/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c1 // SPDX-License-Identifier: GPL-2.0-or-later
60 struct drm_framebuffer *fb = new_plane_state->fb; in hibmc_plane_atomic_check()
61 struct drm_crtc *crtc = new_plane_state->crtc; in hibmc_plane_atomic_check()
63 u32 src_w = new_plane_state->src_w >> 16; in hibmc_plane_atomic_check()
64 u32 src_h = new_plane_state->src_h >> 16; in hibmc_plane_atomic_check()
73 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { in hibmc_plane_atomic_check()
74 drm_dbg_atomic(plane->dev, "scale not support\n"); in hibmc_plane_atomic_check()
75 return -EINVAL; in hibmc_plane_atomic_check()
78 if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0) { in hibmc_plane_atomic_check()
79 drm_dbg_atomic(plane->dev, "crtc_x/y of drm_plane state is invalid\n"); in hibmc_plane_atomic_check()
[all …]
/openbmc/linux/drivers/net/ethernet/ti/
H A Dcpsw-phy-sel.c1 // SPDX-License-Identifier: GPL-2.0
42 u32 reg; in cpsw_gmii_sel_am3352() local
44 u32 mode = 0; in cpsw_gmii_sel_am3352() local
47 reg = readl(priv->gmii_sel); in cpsw_gmii_sel_am3352()
51 mode = AM33XX_GMII_SEL_MODE_RMII; in cpsw_gmii_sel_am3352()
55 mode = AM33XX_GMII_SEL_MODE_RGMII; in cpsw_gmii_sel_am3352()
61 mode = AM33XX_GMII_SEL_MODE_RGMII; in cpsw_gmii_sel_am3352()
66 dev_warn(priv->dev, in cpsw_gmii_sel_am3352()
67 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n", in cpsw_gmii_sel_am3352()
71 mode = AM33XX_GMII_SEL_MODE_MII; in cpsw_gmii_sel_am3352()
[all …]
/openbmc/linux/drivers/media/platform/samsung/s5p-g2d/
H A Dg2d-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Samsung S5P G2D - 2D Graphics Accelerator Driver
10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/genet/
H A Dbcmgenet_wol.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom GENET (Gigabit Ethernet) Wake-on-LAN support
5 * Copyright (c) 2014-2024 Broadcom
37 /* ethtool function - get WOL (Wake on LAN) settings, Only Magic Packet
43 struct device *kdev = &priv->pdev->dev; in bcmgenet_get_wol()
46 if (dev->phydev) { in bcmgenet_get_wol()
47 phy_ethtool_get_wol(dev->phydev, wol); in bcmgenet_get_wol()
48 phy_wolopts = wol->wolopts; in bcmgenet_get_wol()
51 /* MAC is not wake-up capable, return what the PHY does */ in bcmgenet_get_wol()
56 wol->supported |= WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER; in bcmgenet_get_wol()
[all …]
/openbmc/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v1.c125 #include "xgbe-common.h"
127 #define XGBE_BLWC_PROPERTY "amd,serdes-blwc"
128 #define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
129 #define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
130 #define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp"
131 #define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
132 #define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
165 /* Rate-change complete wait/retry count */
234 struct ethtool_link_ksettings *lks = &pdata->phy.lks; in xgbe_phy_an_outcome()
235 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_an_outcome()
[all …]
/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-di.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
125 return readl(di->base + offset); in ipu_di_read()
130 writel(value, di->base + offset); in ipu_di_write()
137 u32 reg; in ipu_di_data_wave_config() local
[all …]
/openbmc/linux/sound/firewire/dice/
H A Ddice-extension.c1 // SPDX-License-Identifier: GPL-2.0
3 * dice-extension.c - a part of driver for DICE based devices
53 return snd_fw_transaction(dice->unit, in read_transaction()
61 unsigned int mode, in read_stream_entries() argument
66 __be32 reg[2]; in read_stream_entries() local
74 reg, sizeof(reg)); in read_stream_entries()
77 pcm_channels[i][mode] = be32_to_cpu(reg[0]); in read_stream_entries()
78 midi_ports[i] = max(midi_ports[i], be32_to_cpu(reg[1])); in read_stream_entries()
87 __be32 reg[2]; in detect_stream_formats() local
89 int mode; in detect_stream_formats() local
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp_cm.c36 #define REG(reg)\ macro
37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
56 //Temp, put CM in bypass mode in dpp2_enable_cm_block()
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); in dpp2_set_degamma_pwl()
136 enum ipp_degamma_mode mode) in dpp2_set_degamma() argument
141 switch (mode) { in dpp2_set_degamma()
183 /* value stored in dbg reg will be 1 greater than mode we want */ in program_gamut_remap()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-zii-scu4-aib.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
5 /dts-v1/;
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
13 stdout-path = &uart0;
18 reg = <0x80000000 0x20000000>;
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-0 = <&pinctrl_leds_debug>;
24 pinctrl-names = "default";
[all …]

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