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/openbmc/linux/drivers/net/
H A Dmii.c3 mii.c: MII interface library
34 #include <linux/mii.h>
36 static u32 mii_get_an(struct mii_if_info *mii, u16 addr) in mii_get_an() argument
40 advert = mii->mdio_read(mii->dev, mii->phy_id, addr); in mii_get_an()
47 * @mii: MII interface
53 void mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) in mii_ethtool_gset() argument
55 struct net_device *dev = mii->dev; in mii_ethtool_gset()
63 if (mii->supports_gmii) in mii_ethtool_gset()
74 ecmd->phy_address = mii->phy_id; in mii_ethtool_gset()
79 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); in mii_ethtool_gset()
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_mdio.c4 Provides Bus interface for MII registers
16 #include <linux/mii.h>
84 unsigned int mii_address = priv->hw->mii.addr; in stmmac_xgmac2_mdio_read()
85 unsigned int mii_data = priv->hw->mii.data; in stmmac_xgmac2_mdio_read()
93 /* Wait until any existing MII operation is complete */ in stmmac_xgmac2_mdio_read()
100 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read()
101 & priv->hw->mii.clk_csr_mask; in stmmac_xgmac2_mdio_read()
104 /* Wait until any existing MII operation is complete */ in stmmac_xgmac2_mdio_read()
111 /* Set the MII address register to read */ in stmmac_xgmac2_mdio_read()
115 /* Wait until any existing MII operation is complete */ in stmmac_xgmac2_mdio_read()
[all …]
/openbmc/linux/drivers/net/mdio/
H A Dmdio-regmap.c56 struct mii_bus *mii; in devm_mdio_regmap_register() local
62 mii = devm_mdiobus_alloc_size(config->parent, sizeof(*mr)); in devm_mdio_regmap_register()
63 if (!mii) in devm_mdio_regmap_register()
66 mr = mii->priv; in devm_mdio_regmap_register()
70 mii->name = DRV_NAME; in devm_mdio_regmap_register()
71 strscpy(mii->id, config->name, MII_BUS_ID_SIZE); in devm_mdio_regmap_register()
72 mii->parent = config->parent; in devm_mdio_regmap_register()
73 mii->read = mdio_regmap_read_c22; in devm_mdio_regmap_register()
74 mii->write = mdio_regmap_write_c22; in devm_mdio_regmap_register()
77 mii->phy_mask = ~BIT(config->valid_addr); in devm_mdio_regmap_register()
[all …]
H A Dmdio-i2c.c384 struct mii_bus *mii; in mdio_i2c_alloc() local
390 mii = mdiobus_alloc(); in mdio_i2c_alloc()
391 if (!mii) in mdio_i2c_alloc()
394 snprintf(mii->id, MII_BUS_ID_SIZE, "i2c:%s", dev_name(parent)); in mdio_i2c_alloc()
395 mii->parent = parent; in mdio_i2c_alloc()
396 mii->priv = i2c; in mdio_i2c_alloc()
405 mdiobus_free(mii); in mdio_i2c_alloc()
409 mii->read_c45 = i2c_mii_read_rollball; in mdio_i2c_alloc()
410 mii->write_c45 = i2c_mii_write_rollball; in mdio_i2c_alloc()
413 mii->read = i2c_mii_read_default_c22; in mdio_i2c_alloc()
[all …]
/openbmc/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mdio.c13 #include <linux/mii.h>
27 #define SXGBE_MII_BUSY 0x00400000 /* mii busy */
49 writel(reg, sp->ioaddr + sp->hw->mii.data); in sxgbe_mdio_ctrl_data()
60 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c45()
74 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c22()
82 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access_c22() local
85 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access_c22()
95 return sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access_c22()
102 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access_c45() local
105 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access_c45()
[all …]
/openbmc/linux/drivers/net/phy/
H A Dmdio_devres.c9 struct mii_bus *mii; member
16 mdiobus_free(dr->mii); in devm_mdiobus_free()
38 dr->mii = mdiobus_alloc_size(sizeof_priv); in devm_mdiobus_alloc_size()
39 if (!dr->mii) { in devm_mdiobus_alloc_size()
45 return dr->mii; in devm_mdiobus_alloc_size()
53 mdiobus_unregister(dr->mii); in devm_mdiobus_unregister()
60 struct mii_bus *mii = match_data; in mdiobus_devres_match() local
62 return mii == res->mii; in mdiobus_devres_match()
68 * @bus: MII bus structure to register
93 dr->mii = bus; in __devm_mdiobus_register()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/pcs/
H A Drenesas,rzn1-miic.yaml7 title: Renesas RZ/N1 MII converter
13 This MII converter is present on the Renesas RZ/N1 SoC family. It is
14 responsible to do MII passthrough or convert it to RMII/RGMII.
34 - description: MII reference clock
37 - description: AHB clock used for the MII converter register interface
47 description: MII Switch PORTIN configuration. This value should use one of
56 "^mii-conv@[0-5]$":
58 description: MII converter port
62 description: MII Converter port number.
147 mii_conv1: mii-conv@1 {
[all …]
/openbmc/linux/drivers/bcma/
H A Ddriver_chipcommon_b.c36 void __iomem *mii = ccb->mii; in bcma_chipco_b_mii_write() local
38 writel(offset, mii + BCMA_CCB_MII_MNG_CTL); in bcma_chipco_b_mii_write()
39 bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100); in bcma_chipco_b_mii_write()
40 writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA); in bcma_chipco_b_mii_write()
41 bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100); in bcma_chipco_b_mii_write()
51 ccb->mii = ioremap(ccb->core->addr_s[1], BCMA_CORE_SIZE); in bcma_core_chipcommon_b_init()
52 if (!ccb->mii) in bcma_core_chipcommon_b_init()
60 if (ccb->mii) in bcma_core_chipcommon_b_free()
61 iounmap(ccb->mii); in bcma_core_chipcommon_b_free()
/openbmc/u-boot/include/
H A Dfsl_mdio.h15 u32 miimcfg; /* MII management configuration reg */
16 u32 miimcom; /* MII management command reg */
17 u32 miimadd; /* MII management address reg */
18 u32 miimcon; /* MII management control reg */
19 u32 miimstat; /* MII management status reg */
20 u32 miimind; /* MII management indication reg */
29 /* MII Management Configuration Register */
34 /* MII Management Command Register */
38 /* MII Management Address Register */
41 /* MII Management Indicator Register */
H A Dfsl_dtsec.h34 u32 miimcfg; /* MII management configuration */
35 u32 miimcom; /* MII management command */
36 u32 miimadd; /* MII management address */
37 u32 miimcon; /* MII management control */
38 u32 miimstat; /* MII management status */
39 u32 miimind; /* MII management indicator */
133 #define IEVENT_MMRD 0x00000400 /* MII management read complete */
134 #define IEVENT_MMWR 0x00000200 /* MII management write complete */
153 #define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */
154 #define IMASK_MMWREN 0x00000200 /* MII management write complete enable */
[all …]
/openbmc/qemu/hw/net/
H A Dallwinner_emac.c34 static void mii_set_link(RTL8201CPState *mii, bool link_ok) in mii_set_link() argument
37 mii->bmsr |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP; in mii_set_link()
38 mii->anlpar |= MII_ANAR_TXFD | MII_ANAR_10FD | MII_ANAR_10 | in mii_set_link()
41 mii->bmsr &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in mii_set_link()
42 mii->anlpar = MII_ANAR_TX; in mii_set_link()
46 static void mii_reset(RTL8201CPState *mii, bool link_ok) in mii_reset() argument
48 mii->bmcr = MII_BMCR_FD | MII_BMCR_AUTOEN | MII_BMCR_SPEED; in mii_reset()
49 mii->bmsr = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | in mii_reset()
51 mii->anar = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | in mii_reset()
53 mii->anlpar = MII_ANAR_TX; in mii_reset()
[all …]
/openbmc/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_mii_cfg.c15 void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg) in icssg_mii_update_ipg() argument
19 if (mii == ICSS_MII0) { in icssg_mii_update_ipg()
28 void icssg_mii_update_mtu(struct regmap *mii_rt, int mii, int mtu) in icssg_mii_update_mtu() argument
31 if (mii == ICSS_MII0) { in icssg_mii_update_mtu()
70 void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if) in icssg_miig_set_interface_mode() argument
74 mask = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE : ICSSG_CFG_MII1_MODE; in icssg_miig_set_interface_mode()
75 shift = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE_SHIFT : ICSSG_CFG_MII1_MODE_SHIFT; in icssg_miig_set_interface_mode()
97 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii) in icssg_rgmii_get_speed() argument
101 if (mii == ICSS_MII1) { in icssg_rgmii_get_speed()
109 u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii) in icssg_rgmii_get_fullduplex() argument
[all …]
/openbmc/linux/include/linux/
H A Dsungem_phy.h21 /* Structure used to statically define an mii/gii based PHY */
70 /* MII definitions missing from mii.h */
77 /* MII BCM5201 MULTIPHY interrupt register */
86 /* MII BCM5201 MULTIPHY register bits */
90 /* MII BCM5221 Additional registers */
99 /* MII BCM5241 Additional registers */
102 /* MII BCM5400 1000-BASET Control register */
106 /* MII BCM5400 AUXCONTROL register */
110 /* MII BCM5400 AUXSTATUS register */
H A Dmii.h3 * linux/mii.h: definitions for MII-compatible transceivers
14 #include <uapi/linux/mii.h>
33 extern int mii_link_ok (struct mii_if_info *mii);
34 extern int mii_nway_restart (struct mii_if_info *mii);
35 extern void mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd);
37 struct mii_if_info *mii, struct ethtool_link_ksettings *cmd);
38 extern int mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd);
40 struct mii_if_info *mii, const struct ethtool_link_ksettings *cmd);
41 extern int mii_check_gmii_support(struct mii_if_info *mii);
42 extern void mii_check_link (struct mii_if_info *mii);
[all …]
H A Dmii_timestamper.h3 * Support for generic time stamping devices on MII buses.
16 * struct mii_timestamper - Callback interface to MII time stamping devices.
19 * the MII time stamping device promises to deliver it using
24 * @txtstamp: Requests a Tx timestamp for 'skb'. The MII time stamping
66 * struct mii_timestamping_ctrl - MII time stamping controller interface.
72 * MII timestamper instance or PTR_ERR.
/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfsl_pq_mdio.c21 #include <linux/mii.h>
41 u32 miimcfg; /* MII management configuration reg */
42 u32 miimcom; /* MII management command reg */
43 u32 miimadd; /* MII management address reg */
44 u32 miimcon; /* MII management control reg */
45 u32 miimstat; /* MII management status reg */
46 u32 miimind; /* MII management indication reg */
56 struct fsl_pq_mii mii; member
62 /* Number of microseconds to wait for an MII register to respond */
74 * @mii_offset: the offset of the MII registers within the memory map of the
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ptp/
H A Dtimestamper.txt1 Time stamps from MII bus snooping devices
3 This binding supports non-PHY devices that snoop the MII bus and
6 alone MII time stamping drivers use this binding to specify the
9 Non-PHY MII time stamping drivers typically talk to the control
12 time stamping channels, each of which snoops on a MII bus.
15 stamping channel from the controller device to that phy's MII bus.
40 In this example, time stamps from the MII bus attached to phy@1 will
/openbmc/linux/drivers/net/usb/
H A Dasix_devices.c69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); in asix_get_phyid()
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); in asix_get_phyid()
104 return mii_link_ok(&dev->mii); in asix_get_link()
111 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); in asix_ioctl()
176 mii_check_media(&dev->mii, 1, 1); in ax88172_link_reset()
177 mii_ethtool_gset(&dev->mii, &ecmd); in ax88172_link_reset()
208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); in asix_phy_reset()
215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) in asix_phy_reset()
223 dev->mii.phy_id); in asix_phy_reset()
[all …]
/openbmc/openbmc/poky/meta/recipes-extended/net-tools/
H A Dnet-tools_2.10.bb84 base_sbindir_progs = "ipmaddr iptunnel mii-tool nameif \
107 NETTOOLS_PACKAGES = "${PN}-mii-tool"
113 FILES:${PN}-mii-tool = "${base_sbindir}/mii-tool"
115 ALTERNATIVE:${PN}:remove = "mii-tool"
117 ALTERNATIVE:${PN}-mii-tool = "mii-tool"
118 ALTERNATIVE_TARGET[mii-tool] = "${base_sbindir}/mii-tool"
119 ALTERNATIVE_LINK_NAME[mii-tool] = "${base_sbindir}/mii-tool"
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-falcon.c136 MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
137 MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
138 MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
139 MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
140 MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
141 MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
142 MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
143 MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
144 MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
145 MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt33 mii(col)
35 mii(crs)
41 mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
43 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
47 mpp35 35 gpio, mii(rxerr)
71 mii(col), mii-1(rxerr)
73 mii(crs), sata0(prsnt)
79 mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
81 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
100 mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
[all …]
/openbmc/u-boot/include/net/
H A Dmdio.h14 * mdio_mii_bus_get() - Get mii bus from mdio udevice
17 * @busp: returns mii bus
32 * mdio_mii_bus_get_from_phy() - Get the mii bus which the phy belongs to
35 * @busp: returns mii bus
54 * function can get the mii bus which the phy belongs to
57 * @busp: returns mii bus
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-boneblack.dts139 "[mii col]",
140 "[mii crs]",
141 "[mii rx err]",
142 "[mii tx en]",
143 "[mii rx dv]",
148 "[mii tx clk]",
149 "[mii rx clk]",
/openbmc/u-boot/doc/
H A DREADME.bitbangMII1 This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
2 support an arbitrary number of mii buses. This feature is useful when your
3 board uses different mii buses for different phys and all (or a part) of these
15 MII_INIT - Generic code to enable the MII bus (optional)
29 the bb_miiphy_buses_num variable with the number of mii buses.
33 char name[] - The symbolic name that must be equal to the MII bus
/openbmc/linux/drivers/net/pcs/
H A DKconfig29 tristate "Renesas RZ/N1 MII converter"
32 This module provides a driver for the MII converter that is available
33 on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
34 pass-through mode for MII.

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