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/openbmc/linux/drivers/mailbox/
H A Darm_mhuv2.c162 * @mbox: Mailbox controller belonging to the MHU frame.
207 int (*rx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
208 void (*rx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
209 void *(*read_data)(struct mhuv2 *mhu, struct mbox_chan *chan);
211 void (*tx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
212 void (*tx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
213 int (*last_tx_done)(struct mhuv2 *mhu, struct mbox_chan *chan);
214 int (*send_data)(struct mhuv2 *mhu, struct mbox_chan *chan, void *arg);
261 static int mhuv2_doorbell_rx_startup(struct mhuv2 *mhu, struct mbox_chan *chan) in mhuv2_doorbell_rx_startup() argument
266 &mhu->recv->ch_wn[priv->ch_wn_idx].mask_clear); in mhuv2_doorbell_rx_startup()
[all …]
H A Darm_mhu_db.c5 * Based on ARM MHU driver by Jassi Brar <jaswinder.singh@linaro.org>
46 * struct mhu_db_channel - ARM MHU Mailbox allocated channel information
48 * @mhu: Pointer to parent mailbox device
53 struct arm_mhu *mhu; member
78 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].rx_reg; in mhu_db_mbox_clear_irq()
83 static unsigned int mhu_db_mbox_irq_to_pchan_num(struct arm_mhu *mhu, int irq) in mhu_db_mbox_irq_to_pchan_num() argument
88 if (mhu->mlink[pchan].irq == irq) in mhu_db_mbox_irq_to_pchan_num()
94 mhu_db_mbox_irq_to_channel(struct arm_mhu *mhu, unsigned int pchan) in mhu_db_mbox_irq_to_channel() argument
99 struct mbox_controller *mbox = &mhu->mbox; in mhu_db_mbox_irq_to_channel()
100 void __iomem *base = mhu->mlink[pchan].rx_reg; in mhu_db_mbox_irq_to_channel()
[all …]
H A Dplatform_mhu.c119 struct platform_mhu *mhu; in platform_mhu_probe() local
126 mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); in platform_mhu_probe()
127 if (!mhu) in platform_mhu_probe()
130 mhu->base = devm_platform_ioremap_resource(pdev, 0); in platform_mhu_probe()
131 if (IS_ERR(mhu->base)) { in platform_mhu_probe()
133 return PTR_ERR(mhu->base); in platform_mhu_probe()
137 mhu->chan[i].con_priv = &mhu->mlink[i]; in platform_mhu_probe()
138 mhu->mlink[i].irq = platform_get_irq(pdev, i); in platform_mhu_probe()
139 if (mhu->mlink[i].irq < 0) in platform_mhu_probe()
140 return mhu->mlink[i].irq; in platform_mhu_probe()
[all …]
H A Darm_mhu.c113 struct arm_mhu *mhu; in mhu_probe() local
117 if (!of_device_is_compatible(dev->of_node, "arm,mhu")) in mhu_probe()
121 mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); in mhu_probe()
122 if (!mhu) in mhu_probe()
125 mhu->base = devm_ioremap_resource(dev, &adev->res); in mhu_probe()
126 if (IS_ERR(mhu->base)) in mhu_probe()
127 return PTR_ERR(mhu->base); in mhu_probe()
130 mhu->chan[i].con_priv = &mhu->mlink[i]; in mhu_probe()
131 mhu->mlink[i].irq = adev->irq[i]; in mhu_probe()
132 mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i]; in mhu_probe()
[all …]
H A DKconfig24 tristate "ARM MHU Mailbox"
27 Say Y here if you want to build the ARM MHU controller driver.
45 tristate "Platform MHU Mailbox"
49 Say Y here if you want to build a platform specific variant MHU
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Darm,mhu.yaml4 $id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml#
7 title: ARM MHU Mailbox Controller
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
14 independent channels/links to communicate with remote processor(s). MHU links
21 The MHU hardware also allows operations in doorbell mode. The MHU drives the
37 - arm,mhu
38 - arm,mhu-doorbell
47 - const: arm,mhu
52 - const: arm,mhu-doorbell
97 compatible = "arm,mhu", "arm,primecell";
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H A Darm,mhuv2.yaml14 The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
20 be written to or read from. If a pair of MHU controllers is implemented
27 An MHU controller must be specified along with the supported transport
39 may be transmitted through a shared memory region, wherein the MHU is used
111 mhu: mailbox@2b1f0000 {
142 mboxes = <&mhu 0 5>; // Channel Window Group 0, doorbell 5.
143 mboxes = <&mhu 1 7>; // Channel Window Group 1, doorbell 7.
144 mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protocol with 1 window.
145 mboxes = <&mhu 3 0>; // Channel Window Group 3, data transfer protocol with 5 windows.
146 mboxes = <&mhu 4 0>; // Channel Window Group 4, data transfer protocol with 7 windows.
[all …]
H A Damlogic,meson-gxbb-mhu.yaml5 $id: http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#
14 The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
16 MHU links are hardwired on a platform. A link raises interrupt for any
24 - amlogic,meson-gxbb-mhu
33 of MHU.
49 compatible = "amlogic,meson-gxbb-mhu";
/openbmc/qemu/hw/misc/
H A Darmsse-mhu.c2 * ARM SSE-200 Message Handling Unit (MHU)
13 * This is a model of the Message Handling Unit (MHU) which is part of the
27 #include "hw/misc/armsse-mhu.h"
87 "SSE MHU: read of write-only register at offset 0x%x\n", in armsse_mhu_read()
94 "SSE MHU read: bad offset 0x%x\n", (int)offset); in armsse_mhu_read()
127 "SSE MHU: write to read-only register at offset 0x%x\n", in armsse_mhu_write()
133 "SSE MHU write: bad offset 0x%x\n", (int)offset); in armsse_mhu_write()
157 .name = "armsse-mhu",
173 s, "armsse-mhu", 0x1000); in armsse_mhu_init()
H A Dtrace-events284 # armsse-mhu.c
285 armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx6…
286 armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRI…
H A Dmeson.build121 system_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c'))
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/
H A D0018-Make-RSS-and-MHU-sizes-compile-time-definitions-user.patch4 Subject: [PATCH] Make RSS and MHU sizes compile-time definitions
7 Replace the hardcoded RSS and MHU compile definitions values with CMake
9 communication payload and the MHU message.
27 +set(COMMS_MHU_MSG_SIZE 0x4500 CACHE STRING "Max message size that can be transfered via MHU")
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0035-corstone1000-purge-U-Boot-specific-DT-nodes.patch38 + { .node_path = "/soc/mhu@1b000000" },
39 + { .node_path = "/soc/mhu@1b010000" },
40 + { .node_path = "/soc/mhu@1b020000" },
41 + { .node_path = "/soc/mhu@1b030000" },
H A D0051-corstone1000-purge-remoteproc-dts-node.patch23 { .node_path = "/soc/mhu@1b010000" },
24 { .node_path = "/soc/mhu@1b020000" },
25 { .node_path = "/soc/mhu@1b030000" },
/openbmc/qemu/include/hw/misc/
H A Darmsse-mhu.h2 * ARM SSE-200 Message Handling Unit (MHU)
13 * This is a model of the Message Handling Unit (MHU) which is part of the
29 #define TYPE_ARMSSE_MHU "armsse-mhu"
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dfujitsu,mb86s70-crg11.txt17 mhu: mhu0@2b1f0000 {
19 compatible = "arm,mhu";
/openbmc/qemu/hw/arm/
H A Darmsse.c488 /* 6, 7: per-CPU MHU interrupts */
502 /* 6, 7: per-CPU MHU interrupts */
807 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); in armsse_init()
808 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); in armsse_init()
1374 * An SSE-200 with only one CPU should have only one MHU created, in armsse_realize()
1375 * with the region where the second MHU usually is being RAZ/WI. in armsse_realize()
1378 * RAZ/WI region instead of the second MHU. in armsse_realize()
1380 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); in armsse_realize()
1382 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { in armsse_realize()
1385 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); in armsse_realize()
[all …]
H A Dmusca.c73 UnimplementedDeviceState mhu[2]; member
472 { "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x100000 }, in musca_init()
473 { "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x100000 }, in musca_init()
/openbmc/qemu/docs/system/arm/
H A Dmusca.rst21 - MHU
/openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/
H A Dsoftware-architecture.rst75 external system and Host (Cortex-A35) can be performed using MHU as transport
180 memory and MHU interrupts as a doorbell for communication between two cores
181 but currently the whole message is forwarded through the MHU channels in Corstone-1000.
/openbmc/qemu/include/hw/arm/
H A Darmsse.h109 #include "hw/misc/armsse-mhu.h"
180 ARMSSEMHU mhu[2]; member
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-security/trusted-services/
H A Dts-arm-platforms.inc22 file://0018-Make-RSS-and-MHU-sizes-compile-time-definitions-user.patch \
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-scmi.dtsi188 compatible = "arm,mhu-doorbell", "arm,primecell";
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gx.dtsi452 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
/openbmc/linux/drivers/firmware/
H A DKconfig18 Cores(AP) and the System Control Processor(SCP). The MHU peripheral

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