Lines Matching full:mhu
488 /* 6, 7: per-CPU MHU interrupts */
502 /* 6, 7: per-CPU MHU interrupts */
807 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); in armsse_init()
808 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); in armsse_init()
1374 * An SSE-200 with only one CPU should have only one MHU created, in armsse_realize()
1375 * with the region where the second MHU usually is being RAZ/WI. in armsse_realize()
1378 * RAZ/WI region instead of the second MHU. in armsse_realize()
1380 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); in armsse_realize()
1382 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { in armsse_realize()
1385 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); in armsse_realize()
1387 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { in armsse_realize()
1397 * Each MHU has an irq line for each CPU: in armsse_realize()
1398 * MHU 0 irq line 0 -> CPU 0 IRQ 6 in armsse_realize()
1399 * MHU 0 irq line 1 -> CPU 1 IRQ 6 in armsse_realize()
1400 * MHU 1 irq line 0 -> CPU 0 IRQ 7 in armsse_realize()
1401 * MHU 1 irq line 1 -> CPU 1 IRQ 7 in armsse_realize()