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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmctp-i2c-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mctp-i2c-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MCTP I2C transport
10 - Matt Johnston <matt@codeconstruct.com.au>
13 An mctp-i2c-controller defines a local MCTP endpoint on an I2C controller.
14 MCTP I2C is specified by DMTF DSP0237.
16 An mctp-i2c-controller must be attached to an I2C adapter which supports
18 busses) are attached to the mctp-i2c-controller with a 'mctp-controller'
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-yosemite4.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/leds/leds-pca955x.h>
8 #include <dt-bindings/i2c/i2c.h>
12 compatible = "facebook,yosemite4-bmc", "aspeed,ast2600";
44 stdout-path = "serial4:57600n8";
52 iio-hwmon {
53 compatible = "iio-hwmon";
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H A Daspeed-bmc-facebook-greatlakes.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/leds/leds-pca955x.h>
8 #include <dt-bindings/i2c/i2c.h>
12 compatible = "facebook,greatlakes-bmc", "aspeed,ast2600";
23 iio-hwmon {
24 compatible = "iio-hwmon";
25 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
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H A Daspeed-bmc-facebook-harma.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/i2c/i2c.h>
11 compatible = "facebook,harma-bmc", "aspeed,ast2600";
32 stdout-path = &uart5;
40 iio-hwmon {
41 compatible = "iio-hwmon";
42 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
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H A Daspeed-bmc-ampere-mtjefferson.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/gpio/aspeed-gpio.h>
12 compatible = "ampere,mtjefferson-bmc", "aspeed,ast2600";
41 stdout-path = &uart5;
49 reserved-memory {
50 #address-cells = <1>;
51 #size-cells = <1>;
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H A Daspeed-bmc-ampere-mtmitchell.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/gpio/aspeed-gpio.h>
12 compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
27 * i2c bus 30-31 assigned to OCP slot 0-1
33 * i2c bus 32-33 assigned to Riser slot 0-1
39 * i2c bus 38-39 assigned to FRU on Riser slot 0-1
82 stdout-path = &uart5;
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/openbmc/linux/drivers/net/mctp/
H A DKconfig2 if MCTP
4 menu "MCTP Device Drivers"
7 tristate "MCTP serial transport"
11 This driver provides an MCTP-over-serial interface, through a
12 serial line-discipline, as defined by DMTF specification "DSP0253 -
13 MCTP Serial Transport Binding". By attaching the ldisc to a serial
14 device, we get a new net device to transport MCTP packets.
16 This allows communication with external MCTP endpoints which use
18 provide MCTP connectivity between virtual machines, by forwarding
21 Say y here if you need to connect to MCTP endpoints over serial. To
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H A Dmctp-i2c.c1 // SPDX-License-Identifier: GPL-2.0
3 * Management Controller Transport Protocol (MCTP)
5 * "DSP0237 Management Component Transport Protocol (MCTP) SMBus/I2C
9 * A netdev is created for each I2C bus that handles MCTP. In the case of an I2C
11 * shared between all mux I2C busses underneath. For non-mux cases an I2C client
14 * mctp-i2c-controller.yml devicetree binding has further details.
23 #include <linux/i2c-mux.h>
25 #include <net/mctp.h>
31 #define MCTP_I2C_MAXMTU (MCTP_I2C_MAXBLOCK - 1)
41 #define MCTP_I2C_OF_PROP "mctp-controller"
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H A Dmctp-i3c.c1 // SPDX-License-Identifier: GPL-2.0
4 * "DSP0233 Management Component Transport Protocol (MCTP) I3C Transport
17 #include <net/mctp.h>
24 /* 64 byte payload, 4 byte MCTP header */
27 static const int MCTP_I3C_MAXMTU = MCTP_I3C_MAXBUF - 1;
28 /* 4 byte MCTP header, no data, 1 byte PEC */
42 static const char *MCTP_I3C_OF_PROP = "mctp-controller";
64 /* Provisioned ID of our controller */
102 struct i3c_priv_xfer xfer = { .rnw = 1, .len = mi->mrl }; in mctp_i3c_read()
103 struct net_device_stats *stats = &mi->mbus->ndev->stats; in mctp_i3c_read()
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/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md1 # Management Component Transport Protocol (MCTP) LPC Transport Binding Specification for ASPEED BMC…
5 This design provides an efficient method to transfer MCTP packets between the
13 1. DMTF DSP0236, Management Component Transport Protocol (MCTP) Base
18 …<https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-spec…
28 Defined by the MCTP base specification as the smallest maximum packet size all
29 MCTP-compliant endpoints must accept.
33 A hardware-defined flag bit in a KCS device's Status Register (STR). The IBF
42 ### KCS: Keyboard-Controller-Style
46 Controller Style" reflects that the register definition was originally used as
47 the legacy "8742" keyboard controller interface in PC architecture computer
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/openbmc/openbmc/meta-evb/meta-evb-arm/meta-evb-fvp-base/
H A DREADME.md1 # meta-fvp-base
3 This layer contains a reference implementation of OpenBMC for Armv-A Base RevC AEM FVP.
6 where the Base FVP represents the management controller which is communicating
7 with the Manageability Control Processor (MCP) over PLDM over MCTP over UART.
15 +-----------------------+
16 +--------------------------+ | Neoverse RD-N2 FVP |
18 | | MCTP over +-------+ +-------+
19 redfish--| /dev/ttyAMA1 |-------------- UART --------------| MCP | | SCP |
20 +--------------------------+ (terminal_1) (terminal_0) +-------+-------+-------+
30 - The MCP exposes a temperature sensor which our image then exposes over redfish
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/openbmc/docs/designs/
H A Dpldm-stack.md5 Created: 2019-01-22
9 On OpenBMC, in-band IPMI is currently the primary industry-standard means of
19 designed to run on standard transport protocols, for e.g. MCTP (also designed by
20 the DMTF). MCTP provides for a common transport layer over several physical
21 channels, by defining hardware bindings. The solution of PLDM over MCTP also
24 PLDM's purpose is to enable all sorts of "inside the box communication": BMC -
25 Host, BMC - BMC, BMC - Network Controller and BMC - Other (for e.g. sensor)
31 efficient access to low-level platform inventory, monitoring, control, event,
48 - Common in-band communication protocol.
50 - Already existing PLDM Type specifications that cover the most common
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H A Dnvmemi-over-smbus.md1 ### NVMe-MI over SMBus
5 Created: 3-8-2019
9 Currently, OpenBMC does not support NVMe drive information. NVMe-MI
17 NVMe-MI specification defines a command called
23 Express Basic Management Command where describe in NVMe-MI specification to
28 (https://nvmexpress.org/wp-content/uploads/NVM_Express_Management_Interface_1_0a_2017.04.08_-_gold.…
36 - Provide a daemon to monitor NVMe drives. Parameters to be monitored are Status
39 - Provide a D-bus interface to allow other services to access data.
40 - Capability of communication over hardware channel I2C to NVMe drives.
41 - Ability to turn the fault LED on/off for each drive by SmartWarnings if the
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/openbmc/docs/designs/mctp/
H A Dmctp-kernel.md1 # OpenBMC in-kernel MCTP
5 Please refer to the [MCTP Overview](mctp.md) document for general MCTP design
8 This document describes a kernel-based implementation of MCTP infrastructure,
9 providing a sockets-based API for MCTP communication within an OpenBMC-based
14 - The MCTP messaging API should be an obvious application of the existing POSIX
17 - Configuration should be simple for a straightforward MCTP endpoint: a single
20 - Infrastructure should be flexible enough to allow for more complex MCTP
23 - each MCTP network (as defined by section 3.2.31 of DSP0236) may consist of
26 - multiple distinct (ie., non-bridged) networks, possibly containing
29 - multiple local EIDs on a single interface, and
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/openbmc/openbmc/meta-facebook/meta-yosemite4/meta-yosemite4n/recipes-kernel/linux/linux-nuvoton/
H A Dyosemite4.cfg9 # SPI controller master driver and spi-gpio
34 # MUX controller for setting UART switch mode
39 # Enable UBIFS for static no-rootfs
60 # MCTP
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c.txt8 -----------------------------
10 - #address-cells - should be <1>. Read more about addresses below.
11 - #size-cells - should be <0>.
12 - compatible - name of I2C bus controller
21 -----------------------------
26 - clock-frequency
29 - i2c-bus
31 devices and non-I2C devices, the 'i2c-bus' subnode can be used for
32 populating I2C devices. If the 'i2c-bus' subnode is present, only
34 '#address-cells' and '#size-cells' must be defined under this subnode
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/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-kernel/linux/linux-aspeed/
H A Dyosemite4.cfg1 # I2C mqueue for mctp
5 # SPI controller master driver and spi-gpio
/openbmc/intel-ipmi-oem/include/
H A Dmanufacturingcommands.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
19 #include <ipmid/api-types.hpp>
21 #include <phosphor-logging/log.hpp>
40 static constexpr const char* ledService = "xyz.openbmc_project.LED.Controller";
76 static constexpr const char* mctpObjPath = "/xyz/openbmc_project/mctp";
77 static constexpr const char* mctpBaseIntf = "xyz.openbmc_project.MCTP.Base";
163 mctp = 0, enumerator
286 return led->getName(); in getLedPropertyName()
332 int mtmTestBeepFd = -1;
/openbmc/qemu/docs/system/arm/
H A Dnuvoton.rst1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
6 servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an
11 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
13 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
16 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
18 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
21 - ``quanta-gbs-bmc`` Quanta GBS server BMC
22 - ``quanta-gsj`` Quanta GSJ server BMC
23 - ``kudo-bmc`` Fii USA Kudo server BMC
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H A Daspeed.rst1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700
9 with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz)
16 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
17 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
18 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
19 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
23 - ``ast2500-evb`` Aspeed AST2500 Evaluation board
24 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
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/openbmc/docs/architecture/
H A Dinterface-overview.md6 - Engineers provide domain expertise in specific areas and learn about use cases
8 - Give BMC administrators and system integrators a simplified view of the BMC's
11 - Management and security folks need everything to work and play together
38 …https://github.com/openbmc/phosphor-dbus-interfaces/blob/master/yaml/xyz/openbmc_project/Control/S…
58 +----------------+ +----------------+
61 | Network -+- LPC ---+- |
62 -+- eth0 -+--PCIe --+- |
63 -+- eth1 -+--UART --+- |
64 | lo -+- I2C ---+- |
65 | -+--I3C ---+- |
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/openbmc/intel-ipmi-oem/src/
H A Dmanufacturingcommands.cpp8 // http://www.apache.org/licenses/LICENSE-2.0
24 #include <phosphor-logging/lg2.hpp>
62 const static constexpr char* pidControlService = "phosphor-pid-control.service";
67 ctx->bus->yield_method_call<>(ctx->yield, ec, specialModeService, in resetMtmTimer()
95 return -1; in getGpioPathForSmSignal()
109 std::string ledName = ledProp->getName(); in ledStoreAndSet()
113 if (false == ledProp->getLock()) in ledStoreAndSet()
120 ledProp->setPrevState(std::get<std::string>(presentState)); in ledStoreAndSet()
121 ledProp->setLock(true); in ledStoreAndSet()
143 if (true == ledProp->getLock()) in ledRevert()
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-mchp-pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
4 * which has I2C controller in one of its downstream functions
6 * Copyright (C) 2021 - 2022 Microchip Technology Inc.
15 #include <linux/i2c-smbus.h>
66 * delay establishes the MCTP T(IDLE_DELAY) period.
198 * CTRL_CUM_TIME_OUT_XK_TICKS defines SMBus Controller Cumulative Time-Out.
199 * SMBus Controller Cumulative Time-Out duration =
207 * TARGET_CUM_TIME_OUT_XK_TICKS defines SMBus Target Cumulative Time-Out duration.
208 * SMBus Target Cumulative Time-Out duration = TARGET_CUM_TIME_OUT_XK_TICKS[7:0] x
336 void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG; in set_sys_lock()
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/openbmc/linux/include/acpi/
H A Dactbl2.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
6 * Copyright (C) 2000 - 2023, Intel Corp.
37 #define ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */
51 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
59 * All tables must be byte-packed to match the ACPI specification, since
69 * essentially useless for dealing with packed data in on-disk formats or
78 * AEST - Arm Error Source Table
89 /* Common Subtable header - one per Node Structure (Subtable) */
246 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
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/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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