Home
last modified time | relevance | path

Searched +full:master +full:- +full:mode (Results 1 – 25 of 1085) sorted by relevance

12345678910>>...44

/openbmc/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
36 # MASTER side ... talking to discrete SPI slave chips including microcontrollers
40 # bool "SPI Master Support"
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
58 comment "SPI Master Controller Drivers"
79 Altera SPI master controller. The SPI master is connected
86 This enables master mode support for the SPIFC (SPI flash
[all …]
H A Dspi-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (c) 2015-2018 Socionext Inc.
6 // Copyright (c) 2018-2019 Linaro Ltd.
108 (SYNQUACER_HSSPI_FIFO_DEPTH - SYNQUACER_HSSPI_FIFO_TX_THRESHOLD)
126 unsigned int mode; member
143 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS); in read_fifo()
147 len = min(len, sspi->rx_words); in read_fifo()
149 switch (sspi->bpw) { in read_fifo()
151 u8 *buf = sspi->rx_buf; in read_fifo()
153 ioread8_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO, in read_fifo()
[all …]
H A Dspi-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx SPI controller driver (master mode only)
10 * 2002-2007 (c) MontaVista Software, Inc.
51 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
67 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
86 bool force_irq; /* force irq to setup master inhibit */
120 if (!xspi->tx_ptr) { in xilinx_spi_tx()
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
125 switch (xspi->bytes_per_word) { in xilinx_spi_tx()
[all …]
H A Dspi-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
2 // spi-uniphier.c - Socionext UniPhier SPI controller driver
4 // Copyright 2016-2018 Socionext Inc.
29 struct spi_master *master; member
41 u16 mode; member
113 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_enable()
115 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_enable()
123 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_disable()
125 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_disable()
130 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); in uniphier_spi_set_mode()
[all …]
H A Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
9 * SPI master mode controller driver, used in STMicroelectronics devices.
74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
77 count = spi_st->words_remaining; in ssc_write_tx_fifo()
80 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
81 if (spi_st->bytes_per_word == 1) { in ssc_write_tx_fifo()
82 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
84 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
85 word = *spi_st->tx_ptr++ | (word << 8); in ssc_write_tx_fifo()
[all …]
H A Dspi-lp8841-rtc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI master driver for ICP DAS LP-8841 RTC
11 * Copyright (C) 2003 - 2007 Paul Mundt
43 data->state |= SPI_LP8841_RTC_CLK; in setsck()
45 data->state &= ~SPI_LP8841_RTC_CLK; in setsck()
46 writeb(data->state, data->iomem); in setsck()
53 data->state |= SPI_LP8841_RTC_MOSI; in setmosi()
55 data->state &= ~SPI_LP8841_RTC_MOSI; in setmosi()
56 writeb(data->state, data->iomem); in setmosi()
62 return ioread8(data->iomem) & SPI_LP8841_RTC_MISO; in getmiso()
[all …]
H A Dspi-npcm-pspi.c1 // SPDX-License-Identifier: GPL-2.0
23 struct spi_master *master; member
33 u16 mode; member
37 #define DRIVER_NAME "npcm-pspi"
70 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_enable()
72 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_enable()
79 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_disable()
81 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_disable()
88 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_enable()
90 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_enable()
[all …]
H A Dspi-mpc52xx-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC52xx PSC in SPI mode driver.
50 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; in mpc52xx_psc_spi_transfer_setup()
52 cs->speed_hz = (t && t->speed_hz) in mpc52xx_psc_spi_transfer_setup()
53 ? t->speed_hz : spi->max_speed_hz; in mpc52xx_psc_spi_transfer_setup()
54 cs->bits_per_word = (t && t->bits_per_word) in mpc52xx_psc_spi_transfer_setup()
55 ? t->bits_per_word : spi->bits_per_word; in mpc52xx_psc_spi_transfer_setup()
56 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; in mpc52xx_psc_spi_transfer_setup()
62 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; in mpc52xx_psc_spi_activate_cs()
63 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); in mpc52xx_psc_spi_activate_cs()
[all …]
/openbmc/linux/drivers/staging/greybus/
H A Dspilib.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2014-2016 Google Inc.
6 * Copyright 2014-2016 Linaro Ltd.
28 u16 mode; member
41 #define GB_SPI_STATE_MSG_ERROR ((void *)-1)
47 return gb_connection_get_data(spi->connection); in get_master_from_spi()
54 data_max -= sizeof(struct gb_spi_transfer_request); in tx_header_fit_operation()
65 data_max -= sizeof(struct gb_spi_transfer_response); in calc_rx_xfer_size()
68 rx_xfer_size = data_max - rx_size; in calc_rx_xfer_size()
86 data_max -= sizeof(struct gb_spi_transfer_request); in calc_tx_xfer_size()
[all …]
/openbmc/linux/Documentation/networking/
H A Dipvlan.rst1 .. SPDX-License-Identifier: GPL-2.0
13 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
14 the master device share the L2 with its slave devices. I have developed this
34 ip link add link <master> name <slave> type ipvlan [ mode MODE ] [ FLAGS ]
36 MODE: l3 (default) | l3s | l2
41 (a) Following will create IPvlan link with eth0 as master in
42 L3 bridge mode::
45 (b) This command will create IPvlan link in L2 bridge mode::
47 bash# ip link add link eth0 name ipvl0 type ipvlan mode l2 bridge
49 (c) This command will create an IPvlan device in L2 private mode::
[all …]
/openbmc/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrx_dap_fasi.h2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
48 /*-------- compilation control switches --------------------------------------*/
53 /*-------- Required includes -------------------------------------------------*/
57 /*-------- Defines, configuring the API --------------------------------------*/
98 #error At least one of short- or long-addressing format must be allowed.
103 * Single/master multi master setting
106 * Comments about SINGLE MASTER/MULTI MASTER modes:
108 * Consider the two sides:1) the master and 2)the slave.
110 * Master:
112 * + single master mode means no use of repeated starts
[all …]
/openbmc/linux/Documentation/networking/device_drivers/ethernet/ti/
H A Dcpsw_switchdev.rst1 .. SPDX-License-Identifier: GPL-2.0
17 ip -d link show dev sw0p1 | grep switchid
23 Dual mac mode
26 - The new (cpsw_new.c) driver is operating in dual-emac mode by default, thus
30 - optimized promiscuous mode: The P0_UNI_FLOOD (both ports) is enabled in
32 So, Ports in promiscuous mode will keep possibility of mcast and vlan
34 to the same bridge, but without enabling "switch" mode, or to different
36 - learning disabled on ports as it make not too much sense for
37 segregated ports - no forwarding in HW.
38 - enabled basic support for devlink.
[all …]
/openbmc/linux/drivers/i3c/
H A Dmaster.c1 // SPDX-License-Identifier: GPL-2.0
28 * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
33 * - enabling/disabling slave events
34 * - re-triggering DAA
35 * - changing the dynamic address of a device
36 * - relinquishing mastership
37 * - ...
45 down_write(&bus->lock); in i3c_bus_maintenance_lock()
49 * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance
59 up_write(&bus->lock); in i3c_bus_maintenance_unlock()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dcortina,gemini-sata-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
28 reset-names:
30 - const: sata0
31 - const: sata1
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-fsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * FSI-attached I2C master algorithm
63 /* mode register */
158 struct fsi_i2c_master *master; member
189 u32 mode = I2C_MODE_ENHANCED, extended_status, watermark; in fsi_i2c_dev_init() local
193 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, &interrupt); in fsi_i2c_dev_init()
197 mode |= FIELD_PREP(I2C_MODE_CLKDIV, I2C_DEFAULT_CLK_DIV); in fsi_i2c_dev_init()
198 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode); in fsi_i2c_dev_init()
202 rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &extended_status); in fsi_i2c_dev_init()
206 i2c->fifo_size = FIELD_GET(I2C_ESTAT_FIFO_SZ, extended_status); in fsi_i2c_dev_init()
[all …]
/openbmc/linux/include/linux/i3c/
H A Dmaster.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor
41 * @master: I3C master that instantiated this device. Will be used to do
43 * @master_priv: master private data assigned to the device. Can be used to
44 * add master specific information
50 struct i3c_master_controller *master; member
61 * struct i2c_dev_boardinfo - I2C device board information
67 * This structure is used to attach board-level information to an I2C device.
77 * struct i2c_dev_desc - I2C device descriptor
87 * using &struct_i3c_master_controller->ops->attach_i2c_dev().
[all …]
/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dext_caps.c1 // SPDX-License-Identifier: BSD-3-Clause
11 #include <linux/i3c/master.h>
26 hci->vendor_mipi_id = readl(base + 0x04); in hci_extcap_hardware_id()
27 hci->vendor_version_id = readl(base + 0x08); in hci_extcap_hardware_id()
28 hci->vendor_product_id = readl(base + 0x0c); in hci_extcap_hardware_id()
30 dev_info(&hci->master.dev, "vendor MIPI ID: %#x\n", hci->vendor_mipi_id); in hci_extcap_hardware_id()
31 dev_info(&hci->master.dev, "vendor version ID: %#x\n", hci->vendor_version_id); in hci_extcap_hardware_id()
32 dev_info(&hci->master.dev, "vendor product ID: %#x\n", hci->vendor_product_id); in hci_extcap_hardware_id()
35 switch (hci->vendor_mipi_id) { in hci_extcap_hardware_id()
37 hci->quirks |= HCI_QUIRK_RAW_CCC; in hci_extcap_hardware_id()
[all …]
H A Dxfer_mode_rate.h1 /* SPDX-License-Identifier: BSD-3-Clause */
7 * Transfer Mode/Rate Table definitions as found in extended capability
16 * Master Transfer Mode Table Fixed Indexes.
19 * obtained from the mode table in the extended capability area.
22 #define XFERMODE_IDX_I3C_SDR 0x00 /* I3C SDR Mode */
23 #define XFERMODE_IDX_I3C_HDR_DDR 0x01 /* I3C HDR-DDR Mode */
24 #define XFERMODE_IDX_I3C_HDR_T 0x02 /* I3C HDR-Ternary Mode */
25 #define XFERMODE_IDX_I3C_HDR_BT 0x03 /* I3C HDR-BT Mode */
26 #define XFERMODE_IDX_I2C 0x08 /* Legacy I2C Mode */
29 * Transfer Mode Table Entry Bits Definitions
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dmipi_dsim.h1 /* SPDX-License-Identifier: GPL-2.0+ */
62 /* MIPI DSI Processor-to-Peripheral transaction types */
111 * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
114 * @eot_disable: enable or disable EoT packet in HS mode.
115 * @auto_vertical_cnt: specifies auto vertical count mode.
116 * in Video mode, the vertical line transition uses line counter
119 * registers.(in command mode, this variable is ignored)
120 * @hse: set horizontal sync event mode.
121 * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
124 * (in mommand mode, this variable is ignored)
[all …]
/openbmc/linux/include/linux/soundwire/
H A Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
29 /* SDW Master Device Number, not supported yet */
75 * enum sdw_slave_status - Slave status
93 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
94 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
104 * enum sdw_command_response - Command response as defined by SDW spec
132 /* block packing mode enum */
163 * enum sdw_port_data_mode: Data Port mode
165 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
[all …]
/openbmc/linux/drivers/ata/
H A Dpata_ftide010.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * struct ftide010 - state container for the Faraday FTIDE010
29 * @master_cbl: master cable type
32 * @master_to_sata0: Gemini SATA bridge: the ATA master is connected
36 * @master_to_sata1: Gemini SATA bridge: the ATA master is connected
48 /* Gemini-specific properties */
62 #define FTIDE010_UDMA_TIMING0 0x12 /* Master */
76 /* Set this bit for UDMA mode 5 and 6 */
98 * pio_active_time: array of 5 elements for T2 timing for Mode 0,
100 * pio_recovery_time: array of 5 elements for T2l timing for Mode 0,
[all …]
/openbmc/u-boot/drivers/i2c/
H A Ddavinci_i2c.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2004-2014
67 #define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
68 #define I2C_CON_MST (1 << 10) /* Master/slave mode */
69 #define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */
71 #define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
72 #define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
/openbmc/linux/Documentation/w1/masters/
H A Domap-hdq.rst2 Kernel driver for omap HDQ/1-wire module
7 HDQ/1-wire controller on the TI OMAP 2430/3430 platforms.
15 The HDQ/1-Wire module of TI OMAP2430/3430 platforms implement the hardware
16 protocol of the master functions of the Benchmark HDQ and the Dallas
17 Semiconductor 1-Wire protocols. These protocols use a single wire for
18 communication between the master (HDQ/1-Wire controller) and the slave
19 (HDQ/1-Wire external compliant device).
21 A typical application of the HDQ/1-Wire module is the communication with battery
24 The controller supports operation in both HDQ and 1-wire mode. The essential
25 difference between the HDQ and 1-wire mode is how the slave device responds to
[all …]
/openbmc/linux/tools/testing/selftests/bpf/prog_tests/
H A Dxdp_bonding.c1 // SPDX-License-Identifier: GPL-2.0
33 static int root_netns_fd = -1;
48 return -1; in setns_by_name()
63 return -1; in get_rx_packets()
85 return -1; in get_rx_packets()
106 return -1; in xdp_attach()
108 if (!ASSERT_LE(skeletons->nlinks+1, MAX_BPF_LINKS, "too many XDP programs attached")) in xdp_attach()
109 return -1; in xdp_attach()
113 return -1; in xdp_attach()
115 skeletons->links[skeletons->nlinks++] = link; in xdp_attach()
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
80 /* Mode/Arbitration Register */
104 /* Local Bus Direct Slave Give Up Bus Mode */
108 /* PCI Request Mode */
110 /* PCI Specification v2.1 Mode */
112 /* PCI Read No Write Mode */
[all …]

12345678910>>...44