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/openbmc/u-boot/drivers/net/
H A Dep93xx_eth.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cirrus Logic EP93xx ethernet MAC / MII driver.
9 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
28 #define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
29 #define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
47 printf(" rx_dq.base %p\n", priv->rx_dq.base); in dump_dev()
48 printf(" rx_dq.current %p\n", priv->rx_dq.current); in dump_dev()
49 printf(" rx_dq.end %p\n", priv->rx_dq.end); in dump_dev()
50 printf(" rx_sq.base %p\n", priv->rx_sq.base); in dump_dev()
51 printf(" rx_sq.current %p\n", priv->rx_sq.current); in dump_dev()
[all …]
/openbmc/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-mac.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 ** asm/bootinfo-mac.h -- Macintosh-specific boot information definitions
11 * Macintosh-specific tags (all __be32)
14 #define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
15 #define BI_MAC_VADDR 0x8001 /* Mac video base address */
16 #define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
17 #define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
18 #define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
19 #define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
20 #define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
[all …]
/openbmc/qemu/include/standard-headers/asm-m68k/
H A Dbootinfo-mac.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 ** asm/bootinfo-mac.h -- Macintosh-specific boot information definitions
11 * Macintosh-specific tags (all __be32)
14 #define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
15 #define BI_MAC_VADDR 0x8001 /* Mac video base address */
16 #define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
17 #define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
18 #define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
19 #define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
20 #define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
[all …]
/openbmc/u-boot/drivers/net/fm/
H A Dtgec.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 /* MAXFRM - maximum frame length */
28 static void tgec_init_mac(struct fsl_enet_mac *mac) in tgec_init_mac() argument
30 struct tgec *regs = mac->base; in tgec_init_mac()
33 out_be32(&regs->imask, IMASK_MASK_ALL); in tgec_init_mac()
36 out_be32(&regs->ievent, IEVENT_CLEAR_ALL); in tgec_init_mac()
39 out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK); in tgec_init_mac()
42 * 1588 disable, insert second mac disable payload length check in tgec_init_mac()
47 out_be32(&regs->command_config, TGEC_CMD_CFG_INIT); in tgec_init_mac()
[all …]
H A Dmemac.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Roy Zang <tie-fei.zang@freescale.com>
7 /* MAXFRM - maximum frame length */
18 static void memac_init_mac(struct fsl_enet_mac *mac) in memac_init_mac() argument
20 struct memac *regs = mac->base; in memac_init_mac()
23 out_be32(&regs->imask, IMASK_MASK_ALL); in memac_init_mac()
26 out_be32(&regs->ievent, IEVENT_CLEAR_ALL); in memac_init_mac()
29 out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK); in memac_init_mac()
32 out_be32(&regs->hashtable_ctrl, 0); in memac_init_mac()
35 static void memac_enable_mac(struct fsl_enet_mac *mac) in memac_enable_mac() argument
[all …]
H A Ddtsec.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
23 /* MAXFRM - maximum frame length register */
26 static void dtsec_init_mac(struct fsl_enet_mac *mac) in dtsec_init_mac() argument
28 struct dtsec *regs = mac->base; in dtsec_init_mac()
31 out_be32(&regs->maccfg1, MACCFG1_SOFT_RST); in dtsec_init_mac()
34 /* clear soft reset, Rx/Tx MAC disable */ in dtsec_init_mac()
35 out_be32(&regs->maccfg1, 0); in dtsec_init_mac()
38 out_be32(&regs->rctrl, RCTRL_INIT); in dtsec_init_mac()
42 out_be32(&regs->tctrl, TCTRL_INIT); in dtsec_init_mac()
[all …]
H A Dfm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
28 void *base; member
106 void *base; /* MAC controller registers base address */ member
109 void (*init_mac)(struct fsl_enet_mac *mac);
110 void (*enable_mac)(struct fsl_enet_mac *mac);
111 void (*disable_mac)(struct fsl_enet_mac *mac);
112 void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
113 void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type,
120 u32 num; /* 0..n-1 for give type */
[all …]
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
40 bus.priv = priv->mac->phyregs; in dtsec_configure_serdes()
41 bool sgmii_2500 = (priv->enet_if == in dtsec_configure_serdes()
80 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) { in dtsec_configure_serdes()
85 struct dtsec *regs = priv->mac->base; in dtsec_configure_serdes()
86 struct tsec_mii_mng *phyregs = priv->mac->phyregs; in dtsec_configure_serdes()
92 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON, in dtsec_configure_serdes()
94 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA, in dtsec_configure_serdes()
96 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, in dtsec_configure_serdes()
[all …]
/openbmc/linux/drivers/staging/vt6655/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Purpose: MAC routines
13 * vt6655_mac_is_reg_bits_off - Test if All test Bits Off
14 * vt6655_mac_set_short_retry_limit - Set 802.11 Short Retry limit
15 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit
16 * vt6655_mac_set_loopback_mode - Set MAC Loopback Mode
17 * vt6655_mac_save_context - Save Context of MAC Registers
18 * vt6655_mac_restore_context - Restore Context of MAC Registers
19 * MACbSoftwareReset - Software Reset MAC
20 * vt6655_mac_safe_rx_off - Turn Off MAC Rx
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_rx.c1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
16 void __iomem *base = priv->base; in mlxbf_gige_enable_multicast_rx() local
19 data = readq(base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_enable_multicast_rx()
21 writeq(data, base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_enable_multicast_rx()
26 void __iomem *base = priv->base; in mlxbf_gige_disable_multicast_rx() local
29 data = readq(base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_disable_multicast_rx()
31 writeq(data, base + MLXBF_GIGE_RX_MAC_FILTER_GENERAL); in mlxbf_gige_disable_multicast_rx()
37 void __iomem *base = priv->base; in mlxbf_gige_enable_mac_rx_filter() local
40 /* Enable MAC receive filter mask for specified index */ in mlxbf_gige_enable_mac_rx_filter()
[all …]
H A Dmlxbf_gige_main.c1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
10 #include <linux/dma-mapping.h>
41 skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2); in mlxbf_gige_alloc_skb()
45 /* Adjust the headroom so that skb->data is naturally aligned to in mlxbf_gige_alloc_skb()
48 addr = (long)skb->data; in mlxbf_gige_alloc_skb()
49 offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) & in mlxbf_gige_alloc_skb()
50 ~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1); in mlxbf_gige_alloc_skb()
51 offset -= addr; in mlxbf_gige_alloc_skb()
56 *buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir); in mlxbf_gige_alloc_skb()
[all …]
/openbmc/linux/crypto/
H A Dccm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * CCM: Counter with CBC-MAC
5 * (C) Copyright IBM Corp. 2007 - Joy Latten <latten@us.ibm.com>
21 struct crypto_ahash_spawn mac; member
25 struct crypto_ahash *mac; member
79 return -EOVERFLOW; in set_msg_len()
82 memcpy(block - csize, (u8 *)&data + 4 - csize, csize); in set_msg_len()
91 struct crypto_skcipher *ctr = ctx->ctr; in crypto_ccm_setkey()
92 struct crypto_ahash *mac = ctx->mac; in crypto_ccm_setkey() local
102 crypto_ahash_clear_flags(mac, CRYPTO_TFM_REQ_MASK); in crypto_ccm_setkey()
[all …]
/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.c4 * Copyright (c) 2011-2013 AdaCore
41 {0x05C, "FIFO_RX_ALARM_SHUTOFF", "FIFO receive alarm shut-off threshold register", ACC_RW, 0x00000…
44 {0x09C, "FIFO_TX_STARVE_SHUTOFF", "FIFO transmit starve shut-off register", ACC_RW, 0x00000…
53 {0x140, "TR03WT", "TxBD Rings 0-3 round-robin weightings", ACC_RW, 0x00000000},
54 {0x144, "TR47WT", "TxBD Rings 4-7 round-robin weightings", ACC_RW, 0x00000000},
64 {0x200, "TBASEH", "TxBD base address high bits", ACC_RW, 0x00000000},
65 {0x204, "TBASE0", "TxBD base address of ring 0", ACC_RW, 0x00000000},
66 {0x20C, "TBASE1", "TxBD base address of ring 1", ACC_RW, 0x00000000},
67 {0x214, "TBASE2", "TxBD base address of ring 2", ACC_RW, 0x00000000},
68 {0x21C, "TBASE3", "TxBD base address of ring 3", ACC_RW, 0x00000000},
[all …]
/openbmc/linux/Documentation/devicetree/bindings/nvmem/layouts/
H A Dkontron,sl28-vpd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/kontron,sl28-vpd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVMEM layout of the Kontron SMARC-sAL28 vital product data
10 - Michael Walle <michael@walle.cc>
14 number and a base MAC address. The actual MAC addresses for the
15 on-board ethernet devices are derived from this base MAC address by
22 const: kontron,sl28-vpd
24 serial-number:
[all …]
H A Dfixed-cell.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/fixed-cell.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <rafal@milecki.pl>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
16 - const: mac-base
18 Cell with base MAC address to be used for calculating extra relative
27 $ref: /schemas/types.yaml#/definitions/uint32-array
29 - minimum: 0
[all …]
/openbmc/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac-mac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 /* Qualcomm Technologies, Inc. EMAC Ethernet Controller MAC layer support
18 #include "emac-sgmii.h"
210 #define EMAC_SKB_CB(skb) ((struct emac_skb_cb *)(skb)->cb)
234 #define EMAC_RRD(RXQ, SIZE, IDX) ((RXQ)->rrd.v_addr + (SIZE * (IDX)))
235 #define EMAC_RFD(RXQ, SIZE, IDX) ((RXQ)->rfd.v_addr + (SIZE * (IDX)))
236 #define EMAC_TPD(TXQ, SIZE, IDX) ((TXQ)->tpd.v_addr + (SIZE * (IDX)))
238 #define GET_RFD_BUFFER(RXQ, IDX) (&((RXQ)->rfd.rfbuff[(IDX)]))
239 #define GET_TPD_BUFFER(RTQ, IDX) (&((RTQ)->tpd.tpbuff[(IDX)]))
[all …]
/openbmc/openbmc/meta-google/recipes-google/networking/files/
H A Dgbmc-mac-config.sh.in8 # http://www.apache.org/licenses/LICENSE-2.0
16 # shellcheck source=meta-google/recipes-google/ipmi/ipmi-fru-sh/lib.sh
17 source /usr/share/ipmi-fru/lib.sh || exit
29 # Our MAC Address configuration lives in the internal area with a format
32 # 1 Type (Always 1 for MAC Address)
34 # 3-8 MAC Address Base Octets
35 # 9 Num Allocate MACs from Base
36 # 10-30 Padding (Always 0xFF)
41 echo "Not a MAC internal region" >&2
44 mac=("${internal[@]:3:6}")
[all …]
/openbmc/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
12 #include <linux/dma-mapping.h>
56 void __iomem *base; member
116 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
120 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
122 priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
134 return -EIO; in ftgmac100_reset_mac()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
[all …]
H A Dhisilicon-femac.txt1 Hisilicon Fast Ethernet MAC controller
4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
9 The first region is the MAC core register base and size.
10 The second region is the global MAC control register.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
[all …]
H A Dcpsw.txt2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
[all …]
/openbmc/linux/drivers/net/ethernet/amd/
H A Dau1000_eth.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2001-2003, 2006 MontaVista Software Inc.
8 * Added ethtool/mii-tool support,
11 * or riemer@riemer-nt.de: fixed the link beat detection with
14 * converted to use linux-2.6.x's PHY framework
22 #include <linux/dma-mapping.h>
67 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
73 /* AU1000 MAC registers and bits */
202 * make sure there's no out-of-order writes, and that all writes
207 * board-specific configurations
[all …]
/openbmc/u-boot/doc/imx/common/
H A Dimx6.txt1 U-Boot for Freescale i.MX6
3 This file contains information for the port of U-Boot to the Freescale i.MX6
7 -----------------------------------
9 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
11 For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address
17 For reading the MAC address fuses on a MX6Q:
19 - The MAC address is stored in two fuse addresses (the fuse addresses are
22 0x620[31:0] - MAC_ADDR[31:0]
23 0x630[15:0] - MAC_ADDR[47:32]
28 Fuse address for the lower MAC address: 0x620
[all …]
/openbmc/linux/drivers/net/ethernet/rdc/
H A Dr6040.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RDC R6040 Fast Ethernet MAC support
7 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
8 * Copyright (C) 2007-2012 Florian Fainelli <f.fainelli@gmail.com>
43 /* RDC MAC I/O Size */
46 /* MAX RDC MAC */
49 /* MAC registers */
57 #define MAC_RST 0x0001 /* Reset the MAC */
62 #define TM2TX 0x0001 /* Trigger MAC to transmit */
66 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
[all …]
/openbmc/linux/Documentation/networking/dsa/
H A Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]

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