Home
last modified time | relevance | path

Searched full:lpddr4 (Results 1 – 25 of 36) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr4.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
7 title: LPDDR4 SDRAM compliant to JEDEC JESD209-4
18 - pattern: "^lpddr4-[0-9a-f]{2},[0-9a-f]{4}$"
19 - const: jedec,lpddr4
31 compatible = "lpddr4-ff,0100", "jedec,lpddr4";
H A Djedec,lpddr-channel.yaml23 - jedec,lpddr4-channel
85 const: jedec,lpddr4-channel
89 $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
128 compatible = "jedec,lpddr4-channel";
132 compatible = "lpddr4-05,0301", "jedec,lpddr4";
140 compatible = "lpddr4-05,0301", "jedec,lpddr4";
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml91 srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
225 When the DRAM type is LPDDR4, this parameter defines the ODT disable
233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
249 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
257 When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
265 When the DRAM type is LPDDR4, this parameter defines the PHY side clock
273 When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
281 When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
308 srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only.
H A Dnvidia,tegra186-mc.yaml15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A DKconfig5 bool "imx8m lpddr4"
8 Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
H A Dlpddr4_init.c30 debug("DDRINFO: start lpddr4 ddr init\n"); in ddr_init()
90 reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ in ddr_init()
107 /* step8 Configure LPDDR4 PHY's registers */ in ddr_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dlpddr4_define.h53 /* for LPDDR4 Rtt */
62 /* for LPDDR4 Ron */
/openbmc/u-boot/include/configs/
H A Dimx8qxp_mek.h143 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
155 /* LPDDR4 board total DDR is 3GB */
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3399.c166 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
305 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
306 /* LPDDR4 */ in phy_io_config()
398 if (sdram_params->base.dramtype == LPDDR4) in phy_io_config()
865 if (sdram_params->base.dramtype == LPDDR4) { in data_training()
879 /* ca training(LPDDR4,LPDDR3 support) */ in data_training()
883 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ in data_training()
887 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ in data_training()
891 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ in data_training()
895 /* wdq leveling(LPDDR4 support) */ in data_training()
[all …]
/openbmc/linux/arch/arm64/boot/dts/apple/
H A Dt8112-pmgr.dtsi530 apple,always-on; /* LPDDR4 interface */
539 apple,always-on; /* LPDDR4 interface */
548 apple,always-on; /* LPDDR4 interface */
557 apple,always-on; /* LPDDR4 interface */
566 apple,always-on; /* LPDDR4 interface */
575 apple,always-on; /* LPDDR4 interface */
584 apple,always-on; /* LPDDR4 interface */
593 apple,always-on; /* LPDDR4 interface */
H A Dt8103-pmgr.dtsi576 apple,always-on; /* LPDDR4 interface */
585 apple,always-on; /* LPDDR4 interface */
594 apple,always-on; /* LPDDR4 interface */
603 apple,always-on; /* LPDDR4 interface */
744 apple,always-on; /* LPDDR4 interface */
753 apple,always-on; /* LPDDR4 interface */
762 apple,always-on; /* LPDDR4 interface */
771 apple,always-on; /* LPDDR4 interface */
/openbmc/linux/Documentation/devicetree/bindings/soc/renesas/
H A Drenesas,rzv2m-pwc.yaml13 - on/off signal generation for the LPDDR4 core power supply (LPVDD)
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A DREADME24 $ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3399.h13 LPDDR4 = 0x7, enumerator
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drenesas,raa215300.yaml15 and LPDDR4 memory power requirements. The internally compensated regulators,
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-evkb.dts75 /* NVCC_DRAM for LPDDR4 */
/openbmc/linux/drivers/memory/
H A Dbrcmstb_memc.c93 * Cannot change the inactivity timeout on LPDDR4 chips because the in srpd_store()
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsda660-inforce-ifc6560.dts298 /* This gives power to the LPDDR4: never turn it off! */
H A Dsdm660-xiaomi-lavender.dts323 /* This gives power to the LPDDR4: never turn it off! */
H A Dsdm630-sony-xperia-nile.dtsi529 /* This gives power to the LPDDR4: never turn it off! */
/openbmc/linux/drivers/i2c/
H A Di2c-smbus.c427 case 0x1E: /* LPDDR4 */ in i2c_register_spd()
/openbmc/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c1237 * LPDDR4 section A. in tegra210_emc_r21021_set_clock()
1258 * LPDDR4 and DDR3 common section. in tegra210_emc_r21021_set_clock()
1489 * LPDDR4 Conditional Training Kickoff. Removed. in tegra210_emc_r21021_set_clock()
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c35 DRAM_TYPE_STR(LPDDR4), in intel_dram_type_str()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c51 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement…
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_object.c1056 "LPDDR4",

12