1*a4be90ffSFlorian Fainelli // SPDX-License-Identifier: GPL-2.0-only
2*a4be90ffSFlorian Fainelli /*
3*a4be90ffSFlorian Fainelli * DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
4*a4be90ffSFlorian Fainelli *
5*a4be90ffSFlorian Fainelli */
6*a4be90ffSFlorian Fainelli
7*a4be90ffSFlorian Fainelli #include <linux/init.h>
8*a4be90ffSFlorian Fainelli #include <linux/io.h>
9*a4be90ffSFlorian Fainelli #include <linux/kernel.h>
10*a4be90ffSFlorian Fainelli #include <linux/module.h>
11*a4be90ffSFlorian Fainelli #include <linux/of_device.h>
12*a4be90ffSFlorian Fainelli #include <linux/platform_device.h>
13*a4be90ffSFlorian Fainelli
14*a4be90ffSFlorian Fainelli #define REG_MEMC_CNTRLR_CONFIG 0x00
15*a4be90ffSFlorian Fainelli #define CNTRLR_CONFIG_LPDDR4_SHIFT 5
16*a4be90ffSFlorian Fainelli #define CNTRLR_CONFIG_MASK 0xf
17*a4be90ffSFlorian Fainelli #define REG_MEMC_SRPD_CFG_21 0x20
18*a4be90ffSFlorian Fainelli #define REG_MEMC_SRPD_CFG_20 0x34
19*a4be90ffSFlorian Fainelli #define REG_MEMC_SRPD_CFG_1x 0x3c
20*a4be90ffSFlorian Fainelli #define INACT_COUNT_SHIFT 0
21*a4be90ffSFlorian Fainelli #define INACT_COUNT_MASK 0xffff
22*a4be90ffSFlorian Fainelli #define SRPD_EN_SHIFT 16
23*a4be90ffSFlorian Fainelli
24*a4be90ffSFlorian Fainelli struct brcmstb_memc_data {
25*a4be90ffSFlorian Fainelli u32 srpd_offset;
26*a4be90ffSFlorian Fainelli };
27*a4be90ffSFlorian Fainelli
28*a4be90ffSFlorian Fainelli struct brcmstb_memc {
29*a4be90ffSFlorian Fainelli struct device *dev;
30*a4be90ffSFlorian Fainelli void __iomem *ddr_ctrl;
31*a4be90ffSFlorian Fainelli unsigned int timeout_cycles;
32*a4be90ffSFlorian Fainelli u32 frequency;
33*a4be90ffSFlorian Fainelli u32 srpd_offset;
34*a4be90ffSFlorian Fainelli };
35*a4be90ffSFlorian Fainelli
brcmstb_memc_uses_lpddr4(struct brcmstb_memc * memc)36*a4be90ffSFlorian Fainelli static int brcmstb_memc_uses_lpddr4(struct brcmstb_memc *memc)
37*a4be90ffSFlorian Fainelli {
38*a4be90ffSFlorian Fainelli void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG;
39*a4be90ffSFlorian Fainelli u32 reg;
40*a4be90ffSFlorian Fainelli
41*a4be90ffSFlorian Fainelli reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK;
42*a4be90ffSFlorian Fainelli
43*a4be90ffSFlorian Fainelli return reg == CNTRLR_CONFIG_LPDDR4_SHIFT;
44*a4be90ffSFlorian Fainelli }
45*a4be90ffSFlorian Fainelli
brcmstb_memc_srpd_config(struct brcmstb_memc * memc,unsigned int cycles)46*a4be90ffSFlorian Fainelli static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc,
47*a4be90ffSFlorian Fainelli unsigned int cycles)
48*a4be90ffSFlorian Fainelli {
49*a4be90ffSFlorian Fainelli void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset;
50*a4be90ffSFlorian Fainelli u32 val;
51*a4be90ffSFlorian Fainelli
52*a4be90ffSFlorian Fainelli /* Max timeout supported in HW */
53*a4be90ffSFlorian Fainelli if (cycles > INACT_COUNT_MASK)
54*a4be90ffSFlorian Fainelli return -EINVAL;
55*a4be90ffSFlorian Fainelli
56*a4be90ffSFlorian Fainelli memc->timeout_cycles = cycles;
57*a4be90ffSFlorian Fainelli
58*a4be90ffSFlorian Fainelli val = (cycles << INACT_COUNT_SHIFT) & INACT_COUNT_MASK;
59*a4be90ffSFlorian Fainelli if (cycles)
60*a4be90ffSFlorian Fainelli val |= BIT(SRPD_EN_SHIFT);
61*a4be90ffSFlorian Fainelli
62*a4be90ffSFlorian Fainelli writel_relaxed(val, cfg);
63*a4be90ffSFlorian Fainelli /* Ensure the write is committed to the controller */
64*a4be90ffSFlorian Fainelli (void)readl_relaxed(cfg);
65*a4be90ffSFlorian Fainelli
66*a4be90ffSFlorian Fainelli return 0;
67*a4be90ffSFlorian Fainelli }
68*a4be90ffSFlorian Fainelli
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)69*a4be90ffSFlorian Fainelli static ssize_t frequency_show(struct device *dev,
70*a4be90ffSFlorian Fainelli struct device_attribute *attr, char *buf)
71*a4be90ffSFlorian Fainelli {
72*a4be90ffSFlorian Fainelli struct brcmstb_memc *memc = dev_get_drvdata(dev);
73*a4be90ffSFlorian Fainelli
74*a4be90ffSFlorian Fainelli return sprintf(buf, "%d\n", memc->frequency);
75*a4be90ffSFlorian Fainelli }
76*a4be90ffSFlorian Fainelli
srpd_show(struct device * dev,struct device_attribute * attr,char * buf)77*a4be90ffSFlorian Fainelli static ssize_t srpd_show(struct device *dev,
78*a4be90ffSFlorian Fainelli struct device_attribute *attr, char *buf)
79*a4be90ffSFlorian Fainelli {
80*a4be90ffSFlorian Fainelli struct brcmstb_memc *memc = dev_get_drvdata(dev);
81*a4be90ffSFlorian Fainelli
82*a4be90ffSFlorian Fainelli return sprintf(buf, "%d\n", memc->timeout_cycles);
83*a4be90ffSFlorian Fainelli }
84*a4be90ffSFlorian Fainelli
srpd_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)85*a4be90ffSFlorian Fainelli static ssize_t srpd_store(struct device *dev, struct device_attribute *attr,
86*a4be90ffSFlorian Fainelli const char *buf, size_t count)
87*a4be90ffSFlorian Fainelli {
88*a4be90ffSFlorian Fainelli struct brcmstb_memc *memc = dev_get_drvdata(dev);
89*a4be90ffSFlorian Fainelli unsigned int val;
90*a4be90ffSFlorian Fainelli int ret;
91*a4be90ffSFlorian Fainelli
92*a4be90ffSFlorian Fainelli /*
93*a4be90ffSFlorian Fainelli * Cannot change the inactivity timeout on LPDDR4 chips because the
94*a4be90ffSFlorian Fainelli * dynamic tuning process will also get affected by the inactivity
95*a4be90ffSFlorian Fainelli * timeout, thus making it non functional.
96*a4be90ffSFlorian Fainelli */
97*a4be90ffSFlorian Fainelli if (brcmstb_memc_uses_lpddr4(memc))
98*a4be90ffSFlorian Fainelli return -EOPNOTSUPP;
99*a4be90ffSFlorian Fainelli
100*a4be90ffSFlorian Fainelli ret = kstrtouint(buf, 10, &val);
101*a4be90ffSFlorian Fainelli if (ret < 0)
102*a4be90ffSFlorian Fainelli return ret;
103*a4be90ffSFlorian Fainelli
104*a4be90ffSFlorian Fainelli ret = brcmstb_memc_srpd_config(memc, val);
105*a4be90ffSFlorian Fainelli if (ret)
106*a4be90ffSFlorian Fainelli return ret;
107*a4be90ffSFlorian Fainelli
108*a4be90ffSFlorian Fainelli return count;
109*a4be90ffSFlorian Fainelli }
110*a4be90ffSFlorian Fainelli
111*a4be90ffSFlorian Fainelli static DEVICE_ATTR_RO(frequency);
112*a4be90ffSFlorian Fainelli static DEVICE_ATTR_RW(srpd);
113*a4be90ffSFlorian Fainelli
114*a4be90ffSFlorian Fainelli static struct attribute *dev_attrs[] = {
115*a4be90ffSFlorian Fainelli &dev_attr_frequency.attr,
116*a4be90ffSFlorian Fainelli &dev_attr_srpd.attr,
117*a4be90ffSFlorian Fainelli NULL,
118*a4be90ffSFlorian Fainelli };
119*a4be90ffSFlorian Fainelli
120*a4be90ffSFlorian Fainelli static struct attribute_group dev_attr_group = {
121*a4be90ffSFlorian Fainelli .attrs = dev_attrs,
122*a4be90ffSFlorian Fainelli };
123*a4be90ffSFlorian Fainelli
124*a4be90ffSFlorian Fainelli static const struct of_device_id brcmstb_memc_of_match[];
125*a4be90ffSFlorian Fainelli
brcmstb_memc_probe(struct platform_device * pdev)126*a4be90ffSFlorian Fainelli static int brcmstb_memc_probe(struct platform_device *pdev)
127*a4be90ffSFlorian Fainelli {
128*a4be90ffSFlorian Fainelli const struct brcmstb_memc_data *memc_data;
129*a4be90ffSFlorian Fainelli const struct of_device_id *of_id;
130*a4be90ffSFlorian Fainelli struct device *dev = &pdev->dev;
131*a4be90ffSFlorian Fainelli struct brcmstb_memc *memc;
132*a4be90ffSFlorian Fainelli int ret;
133*a4be90ffSFlorian Fainelli
134*a4be90ffSFlorian Fainelli memc = devm_kzalloc(dev, sizeof(*memc), GFP_KERNEL);
135*a4be90ffSFlorian Fainelli if (!memc)
136*a4be90ffSFlorian Fainelli return -ENOMEM;
137*a4be90ffSFlorian Fainelli
138*a4be90ffSFlorian Fainelli dev_set_drvdata(dev, memc);
139*a4be90ffSFlorian Fainelli
140*a4be90ffSFlorian Fainelli of_id = of_match_device(brcmstb_memc_of_match, dev);
141*a4be90ffSFlorian Fainelli memc_data = of_id->data;
142*a4be90ffSFlorian Fainelli memc->srpd_offset = memc_data->srpd_offset;
143*a4be90ffSFlorian Fainelli
144*a4be90ffSFlorian Fainelli memc->ddr_ctrl = devm_platform_ioremap_resource(pdev, 0);
145*a4be90ffSFlorian Fainelli if (IS_ERR(memc->ddr_ctrl))
146*a4be90ffSFlorian Fainelli return PTR_ERR(memc->ddr_ctrl);
147*a4be90ffSFlorian Fainelli
148*a4be90ffSFlorian Fainelli of_property_read_u32(pdev->dev.of_node, "clock-frequency",
149*a4be90ffSFlorian Fainelli &memc->frequency);
150*a4be90ffSFlorian Fainelli
151*a4be90ffSFlorian Fainelli ret = sysfs_create_group(&dev->kobj, &dev_attr_group);
152*a4be90ffSFlorian Fainelli if (ret)
153*a4be90ffSFlorian Fainelli return ret;
154*a4be90ffSFlorian Fainelli
155*a4be90ffSFlorian Fainelli return 0;
156*a4be90ffSFlorian Fainelli }
157*a4be90ffSFlorian Fainelli
brcmstb_memc_remove(struct platform_device * pdev)158*a4be90ffSFlorian Fainelli static int brcmstb_memc_remove(struct platform_device *pdev)
159*a4be90ffSFlorian Fainelli {
160*a4be90ffSFlorian Fainelli struct device *dev = &pdev->dev;
161*a4be90ffSFlorian Fainelli
162*a4be90ffSFlorian Fainelli sysfs_remove_group(&dev->kobj, &dev_attr_group);
163*a4be90ffSFlorian Fainelli
164*a4be90ffSFlorian Fainelli return 0;
165*a4be90ffSFlorian Fainelli }
166*a4be90ffSFlorian Fainelli
167*a4be90ffSFlorian Fainelli enum brcmstb_memc_hwtype {
168*a4be90ffSFlorian Fainelli BRCMSTB_MEMC_V21,
169*a4be90ffSFlorian Fainelli BRCMSTB_MEMC_V20,
170*a4be90ffSFlorian Fainelli BRCMSTB_MEMC_V1X,
171*a4be90ffSFlorian Fainelli };
172*a4be90ffSFlorian Fainelli
173*a4be90ffSFlorian Fainelli static const struct brcmstb_memc_data brcmstb_memc_versions[] = {
174*a4be90ffSFlorian Fainelli { .srpd_offset = REG_MEMC_SRPD_CFG_21 },
175*a4be90ffSFlorian Fainelli { .srpd_offset = REG_MEMC_SRPD_CFG_20 },
176*a4be90ffSFlorian Fainelli { .srpd_offset = REG_MEMC_SRPD_CFG_1x },
177*a4be90ffSFlorian Fainelli };
178*a4be90ffSFlorian Fainelli
179*a4be90ffSFlorian Fainelli static const struct of_device_id brcmstb_memc_of_match[] = {
180*a4be90ffSFlorian Fainelli {
181*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
182*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
183*a4be90ffSFlorian Fainelli },
184*a4be90ffSFlorian Fainelli {
185*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.0",
186*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V20]
187*a4be90ffSFlorian Fainelli },
188*a4be90ffSFlorian Fainelli {
189*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
190*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
191*a4be90ffSFlorian Fainelli },
192*a4be90ffSFlorian Fainelli {
193*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
194*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
195*a4be90ffSFlorian Fainelli },
196*a4be90ffSFlorian Fainelli {
197*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
198*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
199*a4be90ffSFlorian Fainelli },
200*a4be90ffSFlorian Fainelli {
201*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.5",
202*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
203*a4be90ffSFlorian Fainelli },
204*a4be90ffSFlorian Fainelli {
205*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.6",
206*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
207*a4be90ffSFlorian Fainelli },
208*a4be90ffSFlorian Fainelli {
209*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.7",
210*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
211*a4be90ffSFlorian Fainelli },
212*a4be90ffSFlorian Fainelli {
213*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.8",
214*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
215*a4be90ffSFlorian Fainelli },
216*a4be90ffSFlorian Fainelli {
217*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
218*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
219*a4be90ffSFlorian Fainelli },
220*a4be90ffSFlorian Fainelli {
221*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1",
222*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
223*a4be90ffSFlorian Fainelli },
224*a4be90ffSFlorian Fainelli {
225*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-c.1.0",
226*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
227*a4be90ffSFlorian Fainelli },
228*a4be90ffSFlorian Fainelli {
229*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
230*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
231*a4be90ffSFlorian Fainelli },
232*a4be90ffSFlorian Fainelli {
233*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-c.1.2",
234*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
235*a4be90ffSFlorian Fainelli },
236*a4be90ffSFlorian Fainelli {
237*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-c.1.3",
238*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
239*a4be90ffSFlorian Fainelli },
240*a4be90ffSFlorian Fainelli {
241*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr-rev-c.1.4",
242*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
243*a4be90ffSFlorian Fainelli },
244*a4be90ffSFlorian Fainelli /* default to the original offset */
245*a4be90ffSFlorian Fainelli {
246*a4be90ffSFlorian Fainelli .compatible = "brcm,brcmstb-memc-ddr",
247*a4be90ffSFlorian Fainelli .data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
248*a4be90ffSFlorian Fainelli },
249*a4be90ffSFlorian Fainelli {}
250*a4be90ffSFlorian Fainelli };
251*a4be90ffSFlorian Fainelli
brcmstb_memc_suspend(struct device * dev)252*a4be90ffSFlorian Fainelli static int brcmstb_memc_suspend(struct device *dev)
253*a4be90ffSFlorian Fainelli {
254*a4be90ffSFlorian Fainelli struct brcmstb_memc *memc = dev_get_drvdata(dev);
255*a4be90ffSFlorian Fainelli void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset;
256*a4be90ffSFlorian Fainelli u32 val;
257*a4be90ffSFlorian Fainelli
258*a4be90ffSFlorian Fainelli if (memc->timeout_cycles == 0)
259*a4be90ffSFlorian Fainelli return 0;
260*a4be90ffSFlorian Fainelli
261*a4be90ffSFlorian Fainelli /*
262*a4be90ffSFlorian Fainelli * Disable SRPD prior to suspending the system since that can
263*a4be90ffSFlorian Fainelli * cause issues with other memory clients managed by the ARM
264*a4be90ffSFlorian Fainelli * trusted firmware to access memory.
265*a4be90ffSFlorian Fainelli */
266*a4be90ffSFlorian Fainelli val = readl_relaxed(cfg);
267*a4be90ffSFlorian Fainelli val &= ~BIT(SRPD_EN_SHIFT);
268*a4be90ffSFlorian Fainelli writel_relaxed(val, cfg);
269*a4be90ffSFlorian Fainelli /* Ensure the write is committed to the controller */
270*a4be90ffSFlorian Fainelli (void)readl_relaxed(cfg);
271*a4be90ffSFlorian Fainelli
272*a4be90ffSFlorian Fainelli return 0;
273*a4be90ffSFlorian Fainelli }
274*a4be90ffSFlorian Fainelli
brcmstb_memc_resume(struct device * dev)275*a4be90ffSFlorian Fainelli static int brcmstb_memc_resume(struct device *dev)
276*a4be90ffSFlorian Fainelli {
277*a4be90ffSFlorian Fainelli struct brcmstb_memc *memc = dev_get_drvdata(dev);
278*a4be90ffSFlorian Fainelli
279*a4be90ffSFlorian Fainelli if (memc->timeout_cycles == 0)
280*a4be90ffSFlorian Fainelli return 0;
281*a4be90ffSFlorian Fainelli
282*a4be90ffSFlorian Fainelli return brcmstb_memc_srpd_config(memc, memc->timeout_cycles);
283*a4be90ffSFlorian Fainelli }
284*a4be90ffSFlorian Fainelli
285*a4be90ffSFlorian Fainelli static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_memc_pm_ops, brcmstb_memc_suspend,
286*a4be90ffSFlorian Fainelli brcmstb_memc_resume);
287*a4be90ffSFlorian Fainelli
288*a4be90ffSFlorian Fainelli static struct platform_driver brcmstb_memc_driver = {
289*a4be90ffSFlorian Fainelli .probe = brcmstb_memc_probe,
290*a4be90ffSFlorian Fainelli .remove = brcmstb_memc_remove,
291*a4be90ffSFlorian Fainelli .driver = {
292*a4be90ffSFlorian Fainelli .name = "brcmstb_memc",
293*a4be90ffSFlorian Fainelli .of_match_table = brcmstb_memc_of_match,
294*a4be90ffSFlorian Fainelli .pm = pm_ptr(&brcmstb_memc_pm_ops),
295*a4be90ffSFlorian Fainelli },
296*a4be90ffSFlorian Fainelli };
297*a4be90ffSFlorian Fainelli module_platform_driver(brcmstb_memc_driver);
298*a4be90ffSFlorian Fainelli
299*a4be90ffSFlorian Fainelli MODULE_LICENSE("GPL");
300*a4be90ffSFlorian Fainelli MODULE_AUTHOR("Broadcom");
301*a4be90ffSFlorian Fainelli MODULE_DESCRIPTION("DDR SRPD driver for Broadcom STB chips");
302