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/openbmc/qemu/hw/ppc/
H A Dpnv_lpc.c2 * QEMU PowerPC PowerNV LPC controller
52 /* LPC HC registers */
105 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; in pnv_lpc_dt_xscom()
131 const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc"; in pnv_dt_lpc()
205 * LPC Host Controller registers in pnv_dt_lpc()
207 name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR); in pnv_dt_lpc()
216 "ibm,power9-lpc-controller"))); in pnv_dt_lpc()
218 name = g_strdup_printf("lpc@0"); in pnv_dt_lpc()
234 * with the P9 LPC Controller which uses direct MMIOs.
239 bool pnv_lpc_opb_read(PnvLpcController *lpc, uint32_t addr, in pnv_lpc_opb_read() argument
[all …]
H A Dpnv_adu.c46 * LPC Address Map in Pervasive ADU Workbook in pnv_adu_xscom_read()
49 * XXX: implement as class property, or get from LPC? in pnv_adu_xscom_read()
120 qemu_log_mask(LOG_GUEST_ERROR, "ADU: Unsupported LPC access " in pnv_adu_xscom_write()
125 pnv_lpc_opb_read(adu->lpc, lpc_addr, (void *)&data, lpc_size); in pnv_adu_xscom_write()
145 qemu_log_mask(LOG_GUEST_ERROR, "ADU: Unsupported LPC access " in pnv_adu_xscom_write()
151 pnv_lpc_opb_write(adu->lpc, lpc_addr, (void *)&data, lpc_size); in pnv_adu_xscom_write()
180 assert(adu->lpc); in pnv_adu_realize()
189 DEFINE_PROP_LINK("lpc", PnvADU, lpc, TYPE_PNV_LPC, PnvLpcController *),
/openbmc/qemu/hw/isa/
H A Dlpc_ich9.c58 /* ICH9 LPC PCI to ISA bridge */
74 static void ich9_cc_update(ICH9LPCState *lpc) in ich9_cc_update() argument
95 ich9_cc_update_ir(lpc->irr[slot], in ich9_cc_update()
96 pci_get_word(lpc->chip_config + *offset)); in ich9_cc_update()
106 lpc->irr[30][pci_intx] = pci_intx + 4; in ich9_cc_update()
110 static void ich9_cc_init(ICH9LPCState *lpc) in ich9_cc_init() argument
126 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; in ich9_cc_init()
129 ich9_cc_update(lpc); in ich9_cc_init()
132 static void ich9_cc_reset(ICH9LPCState *lpc) in ich9_cc_reset() argument
134 uint8_t *c = lpc->chip_config; in ich9_cc_reset()
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed-lpc.yaml5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
26 * An LPC Host Interface Controller manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
34 Additionally the state of the LPC controller influences the pinmux
42 - aspeed,ast2400-lpc-v2
43 - aspeed,ast2500-lpc-v2
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/openbmc/linux/drivers/phy/
H A Dphy-lpc18xx-usb-otg.c29 struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy); in lpc18xx_usb_otg_phy_init() local
33 ret = clk_set_rate(lpc->clk, 480000000); in lpc18xx_usb_otg_phy_init()
37 return clk_prepare(lpc->clk); in lpc18xx_usb_otg_phy_init()
42 struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy); in lpc18xx_usb_otg_phy_exit() local
44 clk_unprepare(lpc->clk); in lpc18xx_usb_otg_phy_exit()
51 struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy); in lpc18xx_usb_otg_phy_power_on() local
54 ret = clk_enable(lpc->clk); in lpc18xx_usb_otg_phy_power_on()
59 ret = regmap_update_bits(lpc->reg, LPC18XX_CREG_CREG0, in lpc18xx_usb_otg_phy_power_on()
62 clk_disable(lpc->clk); in lpc18xx_usb_otg_phy_power_on()
71 struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy); in lpc18xx_usb_otg_phy_power_off() local
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/openbmc/linux/drivers/clocksource/
H A Dclksrc_st_lpc.c3 * Clocksource using the Low Power Timer found in the Low Power Controller (LPC)
18 #include <dt-bindings/mfd/st-lpc.h>
55 "clksrc-st-lpc", rate, 300, 32, in st_clksrc_init()
58 pr_err("clksrc-st-lpc: Failed to register clocksource\n"); in st_clksrc_init()
71 pr_err("clksrc-st-lpc: Failed to get LPC clock\n"); in st_clksrc_setup_clk()
76 pr_err("clksrc-st-lpc: Failed to enable LPC clock\n"); in st_clksrc_setup_clk()
81 pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); in st_clksrc_setup_clk()
96 ret = of_property_read_u32(np, "st,lpc-mode", &mode); in st_clksrc_of_register()
98 pr_err("clksrc-st-lpc: An LPC mode must be provided\n"); in st_clksrc_of_register()
102 /* LPC can either run as a Clocksource or in RTC or WDT mode */ in st_clksrc_of_register()
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dst_lpc_wdt.txt1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
33 lpc@fde05000 {
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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Drtc-st-lpc.txt1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dst,stih407-lpc1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../rtc/rtc-st-lpc.txt for RTC options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
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/openbmc/hiomapd/
H A Dlpc.c29 #include "lpc.h"
31 #include <linux/aspeed-lpc-ctrl.h>
33 #define LPC_CTRL_PATH "/dev/aspeed-lpc-ctrl"
47 /* Open LPC Device */ in __lpc_dev_init()
61 MSG_ERR("Couldn't get lpc control buffer size: %s\n", in __lpc_dev_init()
67 /* Map at the top of the 28-bit LPC firmware address space-0 */ in __lpc_dev_init()
96 * lpc_map_flash() - Point the lpc bus mapping to the actual flash device
108 * The mask is because the top nibble is the host LPC FW space, in lpc_map_flash()
117 return 0; /* LPC Bus already points to flash */ in lpc_map_flash()
121 MSG_ERR("Can't point lpc mapping to flash while suspended\n"); in lpc_map_flash()
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/openbmc/phosphor-mboxd/
H A Dmboxd_lpc.c31 #include <linux/aspeed-lpc-ctrl.h>
33 #define LPC_CTRL_PATH "/dev/aspeed-lpc-ctrl"
47 /* Open LPC Device */ in __init_lpc_dev()
61 MSG_ERR("Couldn't get lpc control buffer size: %s\n", in __init_lpc_dev()
67 /* Map at the top of the 28-bit LPC firmware address space-0 */ in __init_lpc_dev()
96 * point_to_flash() - Point the lpc bus mapping to the actual flash device
108 * The mask is because the top nibble is the host LPC FW space, in point_to_flash()
117 return 0; /* LPC Bus already points to flash */ in point_to_flash()
121 MSG_ERR("Can't point lpc mapping to flash while suspended\n"); in point_to_flash()
125 MSG_INFO("Pointing HOST LPC bus at the flash\n"); in point_to_flash()
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/openbmc/openbmc/meta-phosphor/recipes-phosphor/ipmi/
H A Dphosphor-ipmi-flash_git.bb26 # Only one type of p2a or lpc can be enabled.
27 PACKAGECONFIG[aspeed-p2a] = "-Dp2a-type=aspeed-p2a,,,,,aspeed-lpc nuvoton-lpc nuvoton-p2a-vga nuvot…
28 PACKAGECONFIG[aspeed-lpc] = "-Dlpc-type=aspeed-lpc,,,,,aspeed-p2a nuvoton-lpc nuvoton-p2a-vga nuvot…
29 PACKAGECONFIG[nuvoton-lpc] = "-Dlpc-type=nuvoton-lpc,,,,,aspeed-p2a aspeed-lpc nuvoton-p2a-vga nuvo…
30 PACKAGECONFIG[nuvoton-p2a-vga] = "-Dp2a-type=nuvoton-p2a-vga,,,,,aspeed-p2a aspeed-lpc nuvoton-lpc …
31 …voton-p2a-mbox] = "-Dp2a-type=nuvoton-p2a-mbox,,,,,aspeed-p2a aspeed-lpc nuvoton-lpc nuvoton-p2a-v…
/openbmc/linux/Documentation/devicetree/bindings/ipmi/
H A Daspeed,ast2400-kcs-bmc.yaml14 interfaces on the LPC bus for in-band IPMI communication with their host.
43 aspeed,lpc-io-reg:
48 The host CPU LPC IO data and status addresses for the device. For most
52 aspeed,lpc-interrupts:
57 A 2-cell property expressing the LPC SerIRQ number and the interrupt
67 description: The LPC channel number in the controller
95 - aspeed,lpc-io-reg
103 aspeed,lpc-io-reg = <0xca2>;
104 aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md1 # Management Component Transport Protocol (MCTP) LPC Transport Binding Specification for ASPEED BMC…
6 host and BMC over the LPC bus on ASPEED BMC platforms.
17 2. Intel (R) Low Pin Count (LPC) Interface Specification 1.1,
52 ### LPC Bus: Low Pin Count Bus
57 ### LPC FW: LPC Firmware Cycles
59 LPC firmware cycles allow separate boot BIOS firmware memory cycles and
60 application memory cycles with respect to the LPC bus. The ASPEED BMCs allow
61 remapping of the LPC firmware cycles onto arbitrary regions of the BMC's
94 ## MCTP over LPC Transport
101 - A window of the LPC FW address space, where reads and writes are forwarded to
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/openbmc/linux/drivers/soc/aspeed/
H A Daspeed-lpc-ctrl.c17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
110 * The bottom half of HICR7 is the MSB of the HOST LPC in aspeed_lpc_ctrl_ioctl()
167 * addr (host lpc address) is safe regardless of values. This in aspeed_lpc_ctrl_ioctl()
169 * side of the LPC bus. This cannot impact the hosts own in aspeed_lpc_ctrl_ioctl()
170 * memory space by surprise as LPC specific accessors are in aspeed_lpc_ctrl_ioctl()
205 * Enable LPC FHW cycles. This is required for the host to in aspeed_lpc_ctrl_ioctl()
285 if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") && in aspeed_lpc_ctrl_probe()
286 !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") && in aspeed_lpc_ctrl_probe()
287 !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) { in aspeed_lpc_ctrl_probe()
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H A DKconfig8 tristate "ASPEED LPC firmware cycle control"
13 Control LPC firmware cycle mappings through ioctl()s. The driver
15 host LPC read/write region can be buffered.
18 tristate "ASPEED LPC snoop support"
23 Provides a driver to control the LPC snoop interface which
25 the host to an arbitrary LPC I/O port.
/openbmc/hiomapd/Documentation/
H A Dmboxd.md29 lpc.c - Contains the functions for controlling the LPC bus mapping
44 currently suspended and the LPC bus maps the flash
47 currently suspended and the LPC bus maps the flash
50 currently suspended and the LPC bus maps the reserved
53 currently suspended and the LPC bus maps the reserved
90 it at the correct LPC offset for that windows location and the requested flash
97 this window and the host pointed at its location on the LPC bus.
131 After initilisation, the daemon points the LPC mapping to the actual flash
168 SIGHUP - Clear the window cache and point the LPC bus mapping back to
179 the active window has been closed, points the LPC bus mapping back to flash,
/openbmc/qemu/hw/acpi/
H A Dich9.c470 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); in ich9_pm_device_pre_plug_cb() local
478 uint64_t negotiated = lpc->smi_negotiated_features; in ich9_pm_device_pre_plug_cb()
492 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); in ich9_pm_device_plug_cb() local
498 acpi_memory_plug_cb(hotplug_dev, &lpc->pm.acpi_memory_hotplug, in ich9_pm_device_plug_cb()
502 if (lpc->pm.cpu_hotplug_legacy) { in ich9_pm_device_plug_cb()
503 legacy_acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.gpe_cpu, dev, errp); in ich9_pm_device_plug_cb()
505 acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp); in ich9_pm_device_plug_cb()
508 acpi_pcihp_device_plug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug, in ich9_pm_device_plug_cb()
519 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); in ich9_pm_device_unplug_request_cb() local
523 &lpc->pm.acpi_memory_hotplug, dev, in ich9_pm_device_unplug_request_cb()
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H A Dich9_timer.c22 ICH9LPCState *lpc; in ich9_pm_update_swsmi_timer() local
25 lpc = container_of(pm, ICH9LPCState, pm); in ich9_pm_update_swsmi_timer()
27 (pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_3) & 0xc0) >> 6; in ich9_pm_update_swsmi_timer()
63 ICH9LPCState *lpc; in ich9_pm_update_periodic_timer() local
66 lpc = container_of(pm, ICH9LPCState, pm); in ich9_pm_update_periodic_timer()
67 per_smi_sel = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1) & 3; in ich9_pm_update_periodic_timer()
/openbmc/u-boot/arch/x86/include/asm/
H A Dlpc_common.h20 #define LPC_EN 0x82 /* LPC IF Enables Register */
31 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
32 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
33 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
34 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
46 * lpc_common_early_init() - Set up common LPC init
51 * @dev: LPC device (a child of the PCH)
/openbmc/phosphor-mboxd/Documentation/
H A Dmboxd.md30 mboxd_lpc.c - Contains the functions for controlling the LPC bus mapping
45 currently suspended and the LPC bus maps the flash
48 currently suspended and the LPC bus maps the flash
51 currently suspended and the LPC bus maps the reserved
54 currently suspended and the LPC bus maps the reserved
91 it at the correct LPC offset for that windows location and the requested flash
98 this window and the host pointed at its location on the LPC bus.
132 After initilisation, the daemon points the LPC mapping to the actual flash
169 SIGHUP - Clear the window cache and point the LPC bus mapping back to
180 active window has been closed, points the LPC bus mapping back to flash, clears
/openbmc/linux/drivers/bus/
H A Dhisi_lpc.c22 #define DRV_NAME "hisi-lpc"
50 #define LPC_REG_OP_LEN 0x10 /* LPC cycles count per start */
58 /* The minimal nanosecond interval for each query on LPC cycle status */
66 * for extra 256 lpc clocks, so (256 + 13) * 30ns = 8 us. The maximum burst
92 * hisi_lpc_target_in - trigger a series of LPC cycles for read operation
93 * @lpcdev: pointer to hisi lpc device
94 * @para: some parameters used to control the lpc I/O operations
95 * @addr: the lpc I/O target port address
145 * hisi_lpc_target_out - trigger a series of LPC cycles for write operation
146 * @lpcdev: pointer to hisi lpc device
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/openbmc/linux/drivers/watchdog/
H A Dst_lpc_wdt.c3 * ST's LPC Watchdog
23 #include <dt-bindings/mfd/st-lpc.h>
29 /* LPC as WDT */
58 .compatible = "st,stih407-lpc",
129 .identity = "ST LPC WDT",
162 ret = of_property_read_u32(np, "st,lpc-mode", &mode); in st_wdog_probe()
164 dev_err(dev, "An LPC mode must be provided\n"); in st_wdog_probe()
168 /* LPC can either run as a Clocksource or in RTC or WDT mode */ in st_wdog_probe()
236 dev_info(dev, "LPC Watchdog driver registered, reset type is %s", in st_wdog_probe()
291 .name = "st-lpc-wdt",
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/openbmc/qemu/include/hw/ppc/
H A Dpnv_lpc.h2 * QEMU PowerPC PowerNV LPC controller
28 #define TYPE_PNV_LPC "pnv-lpc"
77 /* LPC device IRQ state */
80 /* LPC HC registers */
112 bool pnv_lpc_opb_read(PnvLpcController *lpc, uint32_t addr,
114 bool pnv_lpc_opb_write(PnvLpcController *lpc, uint32_t addr,
117 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dopal-lpc.c3 * PowerNV LPC bus handling.
187 struct lpc_debugfs_entry *lpc = filp->private_data; in lpc_debug_read() local
204 if (lpc->lpc_type == OPAL_LPC_FW) { in lpc_debug_read()
210 rc = opal_lpc_read(opal_lpc_chip_id, lpc->lpc_type, pos, in lpc_debug_read()
224 * respective positions (ie, LPC position). in lpc_debug_read()
229 * IE. If the LPC transaction has bytes B0, B1, B2 and B3 in that in lpc_debug_read()
278 struct lpc_debugfs_entry *lpc = filp->private_data; in lpc_debug_write() local
295 if (lpc->lpc_type == OPAL_LPC_FW) { in lpc_debug_write()
334 rc = opal_lpc_write(opal_lpc_chip_id, lpc->lpc_type, pos, in lpc_debug_write()
374 root = debugfs_create_dir("lpc", arch_debugfs_dir); in opal_lpc_init_debugfs()
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