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/openbmc/linux/kernel/locking/
H A Dlock_events_list.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 LOCK_EVENT(pv_latency_kick) /* Average latency (ns) of vCPU kick */
29 LOCK_EVENT(pv_latency_wake) /* Average latency (ns) of kick-to-wakeup */
30 LOCK_EVENT(pv_lock_stealing) /* # of lock stealing operations */
31 LOCK_EVENT(pv_spurious_wakeup) /* # of spurious wakeups in non-head vCPUs */
35 LOCK_EVENT(pv_wait_node) /* # of vCPU wait's at non-head queue node */
45 LOCK_EVENT(lock_slowpath) /* # of locking ops via MCS lock queue */
59 LOCK_EVENT(rwsem_opt_lock) /* # of opt-acquired write locks */
63 LOCK_EVENT(rwsem_rlock_steal) /* # of read locks by lock stealing */
65 LOCK_EVENT(rwsem_rlock_fail) /* # of failed read lock acquisitions */
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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rc6.c1 // SPDX-License-Identifier: MIT
24 * low-voltage mode when idle, using down to 0V while at this stage. This
30 * among each other with the latency required to enter and leave RC6 and
38 * require higher latency to switch to and wake up.
48 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
53 return rc6_to_gt(rc)->i915; in rc6_to_i915()
59 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable()
68 if (!intel_uc_uses_guc_rc(&gt->uc)) { in gen11_rc6_enable()
73 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen11_rc6_enable()
74 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen11_rc6_enable()
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/openbmc/linux/drivers/nvme/host/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/blk-mq.h>
9 #include <linux/blk-integrity.h>
16 #include <linux/backing-dev.h>
27 #include <linux/nvme-auth.h>
65 "max power saving latency for new devices; use PM QOS to change per device");
84 "primary APST latency tolerance in us");
89 "secondary APST latency tolerance in us");
92 * nvme_wq - hosts nvme related works that are not reset or delete
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/openbmc/linux/drivers/pci/pcie/
H A Daspm.c1 // SPDX-License-Identifier: GPL-2.0
55 u32 aspm_capable:7; /* Capable ASPM state with latency */
101 list_for_each_entry(child, &linkbus->devices, bus_list) in pci_function_0()
102 if (PCI_FUNC(child->devfn) == 0) in pci_function_0()
120 return link->aspm_default; in policy_to_aspm_state()
136 return link->clkpm_default; in policy_to_clkpm_state()
144 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
147 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_set_clkpm_nocheck()
151 link->clkpm_enabled = !!enable; in pcie_set_clkpm_nocheck()
160 if (!link->clkpm_capable || link->clkpm_disable) in pcie_set_clkpm()
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/openbmc/linux/drivers/video/fbdev/riva/
H A Driva_hw.c3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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/openbmc/linux/drivers/net/ethernet/intel/igb/
H A Digb_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
14 /* The 82580 timesync updates the system timer every 8ns by 8ns,
38 * +--------------+ +---+---+------+
40 * +--------------+ +---+---+------+
43 * +----------+---+ +--------------+
45 * +----------+---+ +--------------+
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
79 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82576()
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/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz_ptp.c1 // SPDX-License-Identifier: GPL-2.0
24 /* Sub-nanoseconds-adj,max * sub-nanoseconds / 40ns * 1ns
25 * = (2^30-1) * (2 ^ 32) / 40 ns * 1 ns = 6249999
30 #define KSZ_PTP_INC_NS 40ULL /* HW clock is incremented every 40 ns (by 40) */
85 return -EINVAL; in ksz_ptp_tou_pulse_verify()
89 return -ERANGE; in ksz_ptp_tou_pulse_verify()
100 if ((ts->tv_sec & 0xffffffff) != ts->tv_sec) in ksz_ptp_tou_target_time_set()
101 return -EINVAL; in ksz_ptp_tou_target_time_set()
103 ret = ksz_write32(dev, REG_TRIG_TARGET_NANOSEC, ts->tv_nsec); in ksz_ptp_tou_target_time_set()
107 ret = ksz_write32(dev, REG_TRIG_TARGET_SEC, ts->tv_sec); in ksz_ptp_tou_target_time_set()
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/openbmc/linux/include/linux/
H A Dsched.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 #include <linux/posix-timers.h>
77 * We have two separate sets of flags: task->__state
78 * is about runnability, while task->exit_state are
84 /* Used in tsk->__state: */
90 /* Used in tsk->exit_state: */
94 /* Used in tsk->__state again: */
107 #define TASK_ANY (TASK_STATE_MAX-1)
130 #define task_is_running(task) (READ_ONCE((task)->__state) == TASK_RUNNING)
132 #define task_is_traced(task) ((READ_ONCE(task->jobctl) & JOBCTL_TRACED) != 0)
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/openbmc/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
74 * compute CAS write latency according to DDR4 spec
107 * compute the CAS write latency according to DDR3 spec
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/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
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/openbmc/linux/block/
H A Dblk-iolatency.c1 // SPDX-License-Identifier: GPL-2.0
3 * Block rq-qos base io controller
7 * - It's bio based, so the latency covers the whole block layer in addition to
9 * - We will throttle all IO that comes in here if we need to.
10 * - We use the mean latency over the 100ms window. This is because writes can
13 * - By default there's no throttling, we set the queue_depth to UINT_MAX so
17 * The hierarchy works like the cpu controller does, we track the latency at
19 * queue depth. This means that we only care about our latency targets at the
32 * an average latency of 5ms. If it does then we will throttle the "slow"
44 * number of IO's we're allowed to have in flight. This starts at (u64)-1 down
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H A Dbfq-iosched.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "blk-cgroup-rwstat.h"
29 * Soft real-time applications are extremely more latency sensitive
30 * than interactive ones. Over-raise the weight of the former to
38 * per-actuator data. The current value is hopefully a good upper
46 * struct bfq_service_tree - per ioprio_class service tree.
48 * Each service tree represents a B-WF2Q+ scheduler on its own. Each
50 * bfq_service_tree. All the fields are protected by the queue lock
71 * struct bfq_sched_data - multi-class scheduler.
81 * queue requests are served according to B-WF2Q+.
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H A Dblk-throttle.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "blk-cgroup-rwstat.h"
15 #include "blk-stat.h"
16 #include "blk-throttle.h"
31 #define DFL_LATENCY_TARGET (-1L)
36 * For HD, very small latency comes from sequential IO. Such IO is helpless to
46 /* We measure latency for request size from <= 4k to >= 1M */
50 unsigned long total_latency; /* ns / 1024 */
55 unsigned long latency; /* ns / 1024 */ member
94 return pd_to_blkg(&tg->pd); in tg_to_blkg()
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/openbmc/linux/drivers/net/ethernet/8390/
H A Dlib8390.c1 // SPDX-License-Identifier: GPL-1.0+
5 Written 1992-94 by Donald Becker.
16 This is the chip-specific code for many 8390-based ethernet adaptors.
17 This is not a complete driver, it must be combined with board-specific
23 you have found something that needs changing. -- PG
28 Paul Gortmaker : remove set_bit lock, other cleanups.
33 Paul Gortmaker : rewrite Rx overrun handling as per NS specs.
39 Paul Gortmaker : add kmod support for auto-loading of the 8390
79 /* These are the operational function interfaces to board-specific
88 "page" value uses the 8390's 256-byte pages.
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/openbmc/linux/drivers/cpufreq/
H A Dpowernow-k8.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * (c) 2003-2006 Advanced Micro Devices, Inc.
9 u32 numps; /* number of p-states */
10 u32 batps; /* number of p-states supported on battery */
13 * vid/fid pairings, but are modified during the ->target() call
19 u32 plllock; /* pll lock time, units 1 us */
36 * handle hotplug events - so just point at cpufreq pol->cpus
53 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
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/openbmc/linux/drivers/base/power/
H A Ddomain.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/power/domain.c - Common code related to device power domains.
35 __routine = genpd->dev_ops.callback; \
46 void (*lock)(struct generic_pm_domain *genpd); member
54 mutex_lock(&genpd->mlock); in genpd_lock_mtx()
60 mutex_lock_nested(&genpd->mlock, depth); in genpd_lock_nested_mtx()
65 return mutex_lock_interruptible(&genpd->mlock); in genpd_lock_interruptible_mtx()
70 return mutex_unlock(&genpd->mlock); in genpd_unlock_mtx()
74 .lock = genpd_lock_mtx,
81 __acquires(&genpd->slock) in genpd_lock_spin()
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/openbmc/linux/drivers/usb/core/
H A Dhub.c1 // SPDX-License-Identifier: GPL-2.0
58 #define USB_TP_TRANSMISSION_DELAY 40 /* ns */
59 #define USB_TP_TRANSMISSION_DELAY_MAX 65535 /* ns */
60 #define USB_PING_RESPONSE_TIME 400 /* ns */
69 /* Protect struct usb_device->state and ->children members
70 * Note: Both are also protected by ->dev.sem, except that ->stat
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/openbmc/linux/drivers/platform/x86/intel/pmc/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
25 #include <asm/intel-family.h>
58 return readl(pmc->regbase + reg_offset); in pmc_core_reg_read()
64 writel(val, pmc->regbase + reg_offset); in pmc_core_reg_write()
75 const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2; in pmc_core_adjust_slp_s0_step()
77 if (pmc->map == &adl_reg_map) in pmc_core_adjust_slp_s0_step()
80 return (u64)value * pmc->map->slp_s0_res_counter_step; in pmc_core_adjust_slp_s0_step()
85 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; in set_etr3()
86 const struct pmc_reg_map *map = pmc->map; in set_etr3()
90 if (!map->etr3_offset) in set_etr3()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Dhsx-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
164 …"BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read mis…
167 "ScaleUnit": "1ns"
170 …"BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read mis…
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/openbmc/linux/fs/proc/
H A Dbase.c1 // SPDX-License-Identifier: GPL-2.0
9 * 1999, Al Viro. Rewritten. Now it covers the whole per-process part.
11 * we allocate and fill in-core inodes upon lookup. They don't even
18 * 17-Jan-2005
25 * Embedded Linux Lab - 10LE Instituto Nokia de Tecnologia - INdT
35 * 21-Feb-2005
36 * Embedded Linux Lab - 10LE Instituto Nokia de Tecnologia - INdT
40 * 10-Mar-2005
41 * 10LE Instituto Nokia de Tecnologia - INdT:
62 #include <linux/generic-radix-tree.h>
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/openbmc/linux/drivers/md/
H A Ddm-ps-historical-service-time.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Keeps a time-weighted exponential moving average of the historical
20 * ns, and the weighting is pre-calculated.
25 #include "dm-path-selector.h"
32 #define DM_MSG_PREFIX "multipath historical-service-time"
48 spinlock_t lock; member
59 spinlock_t lock; member
70 * fixed_power - compute: x^n, in O(log n) time
94 result += 1UL << (frac_bits - 1); in fixed_power()
101 x += 1UL << (frac_bits - 1); in fixed_power()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Dspr-metrics.json4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
18 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
156 …"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memor…
159 "ScaleUnit": "1ns"
162 …"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memor…
165 "ScaleUnit": "1ns"
168 …"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memor…
171 "ScaleUnit": "1ns"
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/openbmc/linux/kernel/sched/
H A Dfair.c1 // SPDX-License-Identifier: GPL-2.0
43 #include <linux/memory-tiers.h>
61 * The initial- and re-scaling of tunables is configurable
65 * SCHED_TUNABLESCALING_NONE - unscaled, always *1
66 * SCHED_TUNABLESCALING_LOG - scaled logarithmical, *1+ilog(ncpus)
67 * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus
74 * Minimal preemption granularity for CPU-bound tasks:
108 return -cpu; in arch_asym_cpu_priority()
129 * Amount of runtime to allocate from global (tg) to local (per-cfs_rq) pool
188 lw->weight += inc; in update_load_add()
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/openbmc/linux/drivers/staging/media/ipu3/
H A Dipu3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 - 2018 Intel Corporation
16 #include "ipu3-dmamap.h"
17 #include "ipu3-mmu.h"
25 * pre-allocated buffer size for IMGU dummy buffers. Those
27 * re-allocation when streaming to lower streaming latency.
72 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe]; in imgu_dummybufs_cleanup()
76 &imgu_pipe->queues[i].dmap); in imgu_dummybufs_cleanup()
84 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe]; in imgu_dummybufs_preallocate()
97 &imgu_pipe->queues[i].dmap, size)) { in imgu_dummybufs_preallocate()
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