Lines Matching +full:lock +full:- +full:latency +full:- +full:ns

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  (c) 2003-2006 Advanced Micro Devices, Inc.
9 	u32 numps;  /* number of p-states */
10 	u32 batps;  /* number of p-states supported on battery */
13 	 * vid/fid pairings, but are modified during the ->target() call
19 	u32 plllock; /* pll lock time, units 1 us */
36 	 * handle hotplug events - so just point at cpufreq pol->cpus
53 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
86  * - only 1 entry in the low fid table ( <=1.4GHz )
87  * - lowest entry in the high fid table must be >= 2 * the entry in the
89  * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
91  * - the parts can only step at <= 200 MHz intervals, odd fid values are
93  * - lowest frequency must be >= interprocessor hypertransport link speed
97 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
117 #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
119 #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */