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/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dloongson64v_4core_virtio.dts26 liointc: interrupt-controller@3ff01400 { label
27 compatible = "loongson,liointc-1.0";
48 interrupt-parent = <&liointc>;
65 interrupt-parent = <&liointc>;
82 0x0000 0x0 0x0 0x1 &liointc 0x2 IRQ_TYPE_LEVEL_HIGH
83 0x0800 0x0 0x0 0x1 &liointc 0x3 IRQ_TYPE_LEVEL_HIGH
84 0x1000 0x0 0x0 0x1 &liointc 0x4 IRQ_TYPE_LEVEL_HIGH
85 0x1800 0x0 0x0 0x1 &liointc 0x5 IRQ_TYPE_LEVEL_HIGH
H A Dloongson64g-package.dtsi24 liointc: interrupt-controller@3ff01400 { label
25 compatible = "loongson,liointc-1.0";
46 interrupt-parent = <&liointc>;
57 interrupt-parent = <&liointc>;
H A Dloongson64c-package.dtsi27 liointc: interrupt-controller@3ff01400 { label
28 compatible = "loongson,liointc-1.0";
49 interrupt-parent = <&liointc>;
60 interrupt-parent = <&liointc>;
H A Dloongson64c_8core_rs780e.dts19 interrupt-parent = <&liointc>;
H A Dloongson64c_4core_rs780e.dts19 interrupt-parent = <&liointc>;
H A Dloongson64c_4core_ls7a.dts19 interrupt-parent = <&liointc>;
H A Dloongson64g_4core_ls7a.dts19 interrupt-parent = <&liointc>;
H A Dloongson64-2k1000.dtsi60 compatible = "loongson,liointc-2.0";
80 compatible = "loongson,liointc-2.0";
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,liointc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
23 - loongson,liointc-1.0
24 - loongson,liointc-1.0a
25 - loongson,liointc-2.0
62 If a CPU interrupt line didn't connect with liointc, then keep its
84 - loongson,liointc-2.0
102 compatible = "loongson,liointc-1.0";
H A Dloongson,htvec.yaml51 interrupt-parent = <&liointc>;
H A Dloongson,htpic.yaml55 interrupt-parent = <&liointc>;
/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
25 to LIOINTC, and then CPUINTC::
33 | LIOINTC | <-- | UARTs |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
70 | EIOINTC | | LIOINTC | <-- | UARTs |
97 LIOINTC::
151 - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst13 中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
18 CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的
36 | LIOINTC | <-- | UARTs |
72 | EIOINTC | | LIOINTC | <-- | UARTs |
99 LIOINTC::
153 - LIOINTC：即《龙芯3A5000处理器使用手册》第11.1节所描述的“传统I/O中断”；
/openbmc/linux/drivers/irqchip/
H A Dirq-loongson-liointc.c248 pr_err("loongson-liointc: cannot add IRQ domain\n"); in liointc_init()
253 (node ? node->full_name : "LIOINTC"), in liointc_init()
256 pr_err("loongson-liointc: unable to register IRQ domain\n"); in liointc_init()
334 if (!of_device_is_compatible(node, "loongson,liointc-2.0")) { in liointc_of_init()
359 pr_err("loongson-liointc: No parent_int_map\n"); in liointc_of_init()
371 IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
372 IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
373 IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
H A DMakefile108 obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
/openbmc/qemu/hw/mips/
H A Dloongson3_virt.c490 DeviceState *liointc; in mips_loongson3_virt_init() local
549 liointc = qdev_new("loongson.liointc"); in mips_loongson3_virt_init()
550 sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal); in mips_loongson3_virt_init()
552 sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base); in mips_loongson3_virt_init()
555 qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0), in mips_loongson3_virt_init()
559 qdev_get_gpio_in(liointc, RTC_IRQ)); in mips_loongson3_virt_init()
595 continue; /* Only node-0 can be connected to LIOINTC */ in mips_loongson3_virt_init()
600 sysbus_connect_irq(SYS_BUS_DEVICE(liointc), in mips_loongson3_virt_init()
660 loongson3_virt_devices_init(machine, liointc); in mips_loongson3_virt_init()
/openbmc/qemu/include/hw/intc/
H A Dloongson_liointc.h18 #define TYPE_LOONGSON_LIOINTC "loongson.liointc"
/openbmc/qemu/docs/system/
H A Dtarget-mips.rst77 - LIOINTC as interrupt controller
/openbmc/linux/
H A Dopengrok2.0.log[all...]
H A Dopengrok0.0.log[all...]
H A Dopengrok1.0.log[all...]