1dbb15226SJiaxun Yang // SPDX-License-Identifier: GPL-2.0
2dbb15226SJiaxun Yang /*
3dbb15226SJiaxun Yang * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
4dbb15226SJiaxun Yang * Loongson Local IO Interrupt Controller support
5dbb15226SJiaxun Yang */
6dbb15226SJiaxun Yang
7dbb15226SJiaxun Yang #include <linux/errno.h>
8dbb15226SJiaxun Yang #include <linux/init.h>
9dbb15226SJiaxun Yang #include <linux/types.h>
10dbb15226SJiaxun Yang #include <linux/interrupt.h>
11dbb15226SJiaxun Yang #include <linux/ioport.h>
12dbb15226SJiaxun Yang #include <linux/irqchip.h>
13dbb15226SJiaxun Yang #include <linux/of_address.h>
14dbb15226SJiaxun Yang #include <linux/of_irq.h>
15dbb15226SJiaxun Yang #include <linux/io.h>
16dbb15226SJiaxun Yang #include <linux/smp.h>
17dbb15226SJiaxun Yang #include <linux/irqchip/chained_irq.h>
18dbb15226SJiaxun Yang
19fa84f893SHuacai Chen #ifdef CONFIG_MIPS
2076e0c88dSQing Zhang #include <loongson.h>
21fa84f893SHuacai Chen #else
22fa84f893SHuacai Chen #include <asm/loongson.h>
23fa84f893SHuacai Chen #endif
24dbb15226SJiaxun Yang
25dbb15226SJiaxun Yang #define LIOINTC_CHIP_IRQ 32
26dbb15226SJiaxun Yang #define LIOINTC_NUM_PARENT 4
27b2c4c396SQing Zhang #define LIOINTC_NUM_CORES 4
28dbb15226SJiaxun Yang
29dbb15226SJiaxun Yang #define LIOINTC_INTC_CHIP_START 0x20
30dbb15226SJiaxun Yang
31dbb15226SJiaxun Yang #define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
32dbb15226SJiaxun Yang #define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
33dbb15226SJiaxun Yang #define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
34dbb15226SJiaxun Yang #define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
351d7471b4SJianmin Lv /*
361d7471b4SJianmin Lv * LIOINTC_REG_INTC_POL register is only valid for Loongson-2K series, and
371d7471b4SJianmin Lv * Loongson-3 series behave as noops.
381d7471b4SJianmin Lv */
39dbb15226SJiaxun Yang #define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
40dbb15226SJiaxun Yang #define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
41dbb15226SJiaxun Yang
42dbb15226SJiaxun Yang #define LIOINTC_SHIFT_INTx 4
43dbb15226SJiaxun Yang
44be09ef09SJiaxun Yang #define LIOINTC_ERRATA_IRQ 10
45be09ef09SJiaxun Yang
466fac824fSJiaxun Yang #if defined(CONFIG_MIPS)
476fac824fSJiaxun Yang #define liointc_core_id get_ebase_cpunum()
486fac824fSJiaxun Yang #else
496fac824fSJiaxun Yang #define liointc_core_id get_csr_cpuid()
506fac824fSJiaxun Yang #endif
516fac824fSJiaxun Yang
52dbb15226SJiaxun Yang struct liointc_handler_data {
53dbb15226SJiaxun Yang struct liointc_priv *priv;
54dbb15226SJiaxun Yang u32 parent_int_map;
55dbb15226SJiaxun Yang };
56dbb15226SJiaxun Yang
57dbb15226SJiaxun Yang struct liointc_priv {
58dbb15226SJiaxun Yang struct irq_chip_generic *gc;
59dbb15226SJiaxun Yang struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
60b2c4c396SQing Zhang void __iomem *core_isr[LIOINTC_NUM_CORES];
61dbb15226SJiaxun Yang u8 map_cache[LIOINTC_CHIP_IRQ];
62fc98adb9SHuacai Chen u32 int_pol;
63fc98adb9SHuacai Chen u32 int_edge;
64be09ef09SJiaxun Yang bool has_lpc_irq_errata;
65dbb15226SJiaxun Yang };
66dbb15226SJiaxun Yang
670858ed03SHuacai Chen struct fwnode_handle *liointc_handle;
680858ed03SHuacai Chen
liointc_chained_handle_irq(struct irq_desc * desc)69dbb15226SJiaxun Yang static void liointc_chained_handle_irq(struct irq_desc *desc)
70dbb15226SJiaxun Yang {
71dbb15226SJiaxun Yang struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
72dbb15226SJiaxun Yang struct irq_chip *chip = irq_desc_get_chip(desc);
73dbb15226SJiaxun Yang struct irq_chip_generic *gc = handler->priv->gc;
746fac824fSJiaxun Yang int core = liointc_core_id % LIOINTC_NUM_CORES;
75dbb15226SJiaxun Yang u32 pending;
76dbb15226SJiaxun Yang
77dbb15226SJiaxun Yang chained_irq_enter(chip, desc);
78dbb15226SJiaxun Yang
79b2c4c396SQing Zhang pending = readl(handler->priv->core_isr[core]);
80dbb15226SJiaxun Yang
81be09ef09SJiaxun Yang if (!pending) {
82be09ef09SJiaxun Yang /* Always blame LPC IRQ if we have that bug */
83be09ef09SJiaxun Yang if (handler->priv->has_lpc_irq_errata &&
84c9c73a05SHuacai Chen (handler->parent_int_map & gc->mask_cache &
85be09ef09SJiaxun Yang BIT(LIOINTC_ERRATA_IRQ)))
86be09ef09SJiaxun Yang pending = BIT(LIOINTC_ERRATA_IRQ);
87be09ef09SJiaxun Yang else
88dbb15226SJiaxun Yang spurious_interrupt();
89be09ef09SJiaxun Yang }
90dbb15226SJiaxun Yang
91dbb15226SJiaxun Yang while (pending) {
92dbb15226SJiaxun Yang int bit = __ffs(pending);
93dbb15226SJiaxun Yang
94046a6ee2SMarc Zyngier generic_handle_domain_irq(gc->domain, bit);
95dbb15226SJiaxun Yang pending &= ~BIT(bit);
96dbb15226SJiaxun Yang }
97dbb15226SJiaxun Yang
98dbb15226SJiaxun Yang chained_irq_exit(chip, desc);
99dbb15226SJiaxun Yang }
100dbb15226SJiaxun Yang
liointc_set_bit(struct irq_chip_generic * gc,unsigned int offset,u32 mask,bool set)101dbb15226SJiaxun Yang static void liointc_set_bit(struct irq_chip_generic *gc,
102dbb15226SJiaxun Yang unsigned int offset,
103dbb15226SJiaxun Yang u32 mask, bool set)
104dbb15226SJiaxun Yang {
105dbb15226SJiaxun Yang if (set)
106dbb15226SJiaxun Yang writel(readl(gc->reg_base + offset) | mask,
107dbb15226SJiaxun Yang gc->reg_base + offset);
108dbb15226SJiaxun Yang else
109dbb15226SJiaxun Yang writel(readl(gc->reg_base + offset) & ~mask,
110dbb15226SJiaxun Yang gc->reg_base + offset);
111dbb15226SJiaxun Yang }
112dbb15226SJiaxun Yang
liointc_set_type(struct irq_data * data,unsigned int type)113dbb15226SJiaxun Yang static int liointc_set_type(struct irq_data *data, unsigned int type)
114dbb15226SJiaxun Yang {
115dbb15226SJiaxun Yang struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
116dbb15226SJiaxun Yang u32 mask = data->mask;
117dbb15226SJiaxun Yang unsigned long flags;
118dbb15226SJiaxun Yang
119dbb15226SJiaxun Yang irq_gc_lock_irqsave(gc, flags);
120dbb15226SJiaxun Yang switch (type) {
121dbb15226SJiaxun Yang case IRQ_TYPE_LEVEL_HIGH:
122dbb15226SJiaxun Yang liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
1231d7471b4SJianmin Lv liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
124dbb15226SJiaxun Yang break;
125dbb15226SJiaxun Yang case IRQ_TYPE_LEVEL_LOW:
126dbb15226SJiaxun Yang liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
1271d7471b4SJianmin Lv liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
128dbb15226SJiaxun Yang break;
129dbb15226SJiaxun Yang case IRQ_TYPE_EDGE_RISING:
130dbb15226SJiaxun Yang liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
1311d7471b4SJianmin Lv liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
132dbb15226SJiaxun Yang break;
133dbb15226SJiaxun Yang case IRQ_TYPE_EDGE_FALLING:
134dbb15226SJiaxun Yang liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
1351d7471b4SJianmin Lv liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
136dbb15226SJiaxun Yang break;
137dbb15226SJiaxun Yang default:
138fa03587cSTiezhu Yang irq_gc_unlock_irqrestore(gc, flags);
139dbb15226SJiaxun Yang return -EINVAL;
140dbb15226SJiaxun Yang }
141dbb15226SJiaxun Yang irq_gc_unlock_irqrestore(gc, flags);
142dbb15226SJiaxun Yang
143dbb15226SJiaxun Yang irqd_set_trigger_type(data, type);
144dbb15226SJiaxun Yang return 0;
145dbb15226SJiaxun Yang }
146dbb15226SJiaxun Yang
liointc_suspend(struct irq_chip_generic * gc)147fc98adb9SHuacai Chen static void liointc_suspend(struct irq_chip_generic *gc)
148fc98adb9SHuacai Chen {
149fc98adb9SHuacai Chen struct liointc_priv *priv = gc->private;
150fc98adb9SHuacai Chen
151fc98adb9SHuacai Chen priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);
152fc98adb9SHuacai Chen priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);
153fc98adb9SHuacai Chen }
154fc98adb9SHuacai Chen
liointc_resume(struct irq_chip_generic * gc)155dbb15226SJiaxun Yang static void liointc_resume(struct irq_chip_generic *gc)
156dbb15226SJiaxun Yang {
157dbb15226SJiaxun Yang struct liointc_priv *priv = gc->private;
158dbb15226SJiaxun Yang unsigned long flags;
159dbb15226SJiaxun Yang int i;
160dbb15226SJiaxun Yang
161dbb15226SJiaxun Yang irq_gc_lock_irqsave(gc, flags);
162dbb15226SJiaxun Yang /* Disable all at first */
163dbb15226SJiaxun Yang writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
164c9c73a05SHuacai Chen /* Restore map cache */
165dbb15226SJiaxun Yang for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
166dbb15226SJiaxun Yang writeb(priv->map_cache[i], gc->reg_base + i);
167fc98adb9SHuacai Chen writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);
168fc98adb9SHuacai Chen writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);
169c9c73a05SHuacai Chen /* Restore mask cache */
170c9c73a05SHuacai Chen writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
171dbb15226SJiaxun Yang irq_gc_unlock_irqrestore(gc, flags);
172dbb15226SJiaxun Yang }
173dbb15226SJiaxun Yang
1740858ed03SHuacai Chen static int parent_irq[LIOINTC_NUM_PARENT];
1750858ed03SHuacai Chen static u32 parent_int_map[LIOINTC_NUM_PARENT];
176dbb15226SJiaxun Yang static const char *const parent_names[] = {"int0", "int1", "int2", "int3"};
177b2c4c396SQing Zhang static const char *const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
178b2c4c396SQing Zhang
liointc_domain_xlate(struct irq_domain * d,struct device_node * ctrlr,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1790858ed03SHuacai Chen static int liointc_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
1800858ed03SHuacai Chen const u32 *intspec, unsigned int intsize,
1810858ed03SHuacai Chen unsigned long *out_hwirq, unsigned int *out_type)
182b2c4c396SQing Zhang {
1830858ed03SHuacai Chen if (WARN_ON(intsize < 1))
1840858ed03SHuacai Chen return -EINVAL;
1850858ed03SHuacai Chen *out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
18617343d0bSJianmin Lv
18717343d0bSJianmin Lv if (intsize > 1)
18817343d0bSJianmin Lv *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
18917343d0bSJianmin Lv else
1900858ed03SHuacai Chen *out_type = IRQ_TYPE_NONE;
19117343d0bSJianmin Lv
1920858ed03SHuacai Chen return 0;
193b2c4c396SQing Zhang }
194dbb15226SJiaxun Yang
1950858ed03SHuacai Chen static const struct irq_domain_ops acpi_irq_gc_ops = {
1960858ed03SHuacai Chen .map = irq_map_generic_chip,
1970858ed03SHuacai Chen .unmap = irq_unmap_generic_chip,
1980858ed03SHuacai Chen .xlate = liointc_domain_xlate,
1990858ed03SHuacai Chen };
2000858ed03SHuacai Chen
liointc_init(phys_addr_t addr,unsigned long size,int revision,struct fwnode_handle * domain_handle,struct device_node * node)2010858ed03SHuacai Chen static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
2020858ed03SHuacai Chen struct fwnode_handle *domain_handle, struct device_node *node)
203dbb15226SJiaxun Yang {
2040858ed03SHuacai Chen int i, err;
2050858ed03SHuacai Chen void __iomem *base;
2060858ed03SHuacai Chen struct irq_chip_type *ct;
207dbb15226SJiaxun Yang struct irq_chip_generic *gc;
208dbb15226SJiaxun Yang struct irq_domain *domain;
209dbb15226SJiaxun Yang struct liointc_priv *priv;
210dbb15226SJiaxun Yang
211dbb15226SJiaxun Yang priv = kzalloc(sizeof(*priv), GFP_KERNEL);
212dbb15226SJiaxun Yang if (!priv)
213dbb15226SJiaxun Yang return -ENOMEM;
214dbb15226SJiaxun Yang
2150858ed03SHuacai Chen base = ioremap(addr, size);
2160858ed03SHuacai Chen if (!base)
217b2c4c396SQing Zhang goto out_free_priv;
218dbb15226SJiaxun Yang
219b2c4c396SQing Zhang for (i = 0; i < LIOINTC_NUM_CORES; i++)
220b2c4c396SQing Zhang priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
221dbb15226SJiaxun Yang
222dbb15226SJiaxun Yang for (i = 0; i < LIOINTC_NUM_PARENT; i++)
2230858ed03SHuacai Chen priv->handler[i].parent_int_map = parent_int_map[i];
2240858ed03SHuacai Chen
2250858ed03SHuacai Chen if (revision > 1) {
2260858ed03SHuacai Chen for (i = 0; i < LIOINTC_NUM_CORES; i++) {
2270858ed03SHuacai Chen int index = of_property_match_string(node,
2280858ed03SHuacai Chen "reg-names", core_reg_names[i]);
2290858ed03SHuacai Chen
2300858ed03SHuacai Chen if (index < 0)
2314a60a3cdSLiu Peibao continue;
2320858ed03SHuacai Chen
2330858ed03SHuacai Chen priv->core_isr[i] = of_iomap(node, index);
2340858ed03SHuacai Chen }
2354a60a3cdSLiu Peibao
2364a60a3cdSLiu Peibao if (!priv->core_isr[0])
2374a60a3cdSLiu Peibao goto out_iounmap;
2380858ed03SHuacai Chen }
239dbb15226SJiaxun Yang
240dbb15226SJiaxun Yang /* Setup IRQ domain */
2410858ed03SHuacai Chen if (!acpi_disabled)
2420858ed03SHuacai Chen domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
2430858ed03SHuacai Chen &acpi_irq_gc_ops, priv);
2440858ed03SHuacai Chen else
2450858ed03SHuacai Chen domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
246dbb15226SJiaxun Yang &irq_generic_chip_ops, priv);
247dbb15226SJiaxun Yang if (!domain) {
248dbb15226SJiaxun Yang pr_err("loongson-liointc: cannot add IRQ domain\n");
2490858ed03SHuacai Chen goto out_iounmap;
250dbb15226SJiaxun Yang }
251dbb15226SJiaxun Yang
2520858ed03SHuacai Chen err = irq_alloc_domain_generic_chips(domain, LIOINTC_CHIP_IRQ, 1,
2530858ed03SHuacai Chen (node ? node->full_name : "LIOINTC"),
2540858ed03SHuacai Chen handle_level_irq, 0, IRQ_NOPROBE, 0);
255dbb15226SJiaxun Yang if (err) {
256dbb15226SJiaxun Yang pr_err("loongson-liointc: unable to register IRQ domain\n");
257dbb15226SJiaxun Yang goto out_free_domain;
258dbb15226SJiaxun Yang }
259dbb15226SJiaxun Yang
260dbb15226SJiaxun Yang
261dbb15226SJiaxun Yang /* Disable all IRQs */
262dbb15226SJiaxun Yang writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
263dbb15226SJiaxun Yang /* Set to level triggered */
264dbb15226SJiaxun Yang writel(0x0, base + LIOINTC_REG_INTC_EDGE);
265dbb15226SJiaxun Yang
266dbb15226SJiaxun Yang /* Generate parent INT part of map cache */
267dbb15226SJiaxun Yang for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
268dbb15226SJiaxun Yang u32 pending = priv->handler[i].parent_int_map;
269dbb15226SJiaxun Yang
270dbb15226SJiaxun Yang while (pending) {
271dbb15226SJiaxun Yang int bit = __ffs(pending);
272dbb15226SJiaxun Yang
273dbb15226SJiaxun Yang priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
274dbb15226SJiaxun Yang pending &= ~BIT(bit);
275dbb15226SJiaxun Yang }
276dbb15226SJiaxun Yang }
277dbb15226SJiaxun Yang
278dbb15226SJiaxun Yang for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
279dbb15226SJiaxun Yang /* Generate core part of map cache */
280dbb15226SJiaxun Yang priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
281dbb15226SJiaxun Yang writeb(priv->map_cache[i], base + i);
282dbb15226SJiaxun Yang }
283dbb15226SJiaxun Yang
284dbb15226SJiaxun Yang gc = irq_get_domain_generic_chip(domain, 0);
285dbb15226SJiaxun Yang gc->private = priv;
286dbb15226SJiaxun Yang gc->reg_base = base;
287dbb15226SJiaxun Yang gc->domain = domain;
288fc98adb9SHuacai Chen gc->suspend = liointc_suspend;
289dbb15226SJiaxun Yang gc->resume = liointc_resume;
290dbb15226SJiaxun Yang
291dbb15226SJiaxun Yang ct = gc->chip_types;
292dbb15226SJiaxun Yang ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
293dbb15226SJiaxun Yang ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
294dbb15226SJiaxun Yang ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
295dbb15226SJiaxun Yang ct->chip.irq_mask = irq_gc_mask_disable_reg;
296dbb15226SJiaxun Yang ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
297dbb15226SJiaxun Yang ct->chip.irq_set_type = liointc_set_type;
298*e01f9882SYinbo Zhu ct->chip.flags = IRQCHIP_SKIP_SET_WAKE;
299dbb15226SJiaxun Yang
300c9c73a05SHuacai Chen gc->mask_cache = 0;
301dbb15226SJiaxun Yang priv->gc = gc;
302dbb15226SJiaxun Yang
303dbb15226SJiaxun Yang for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
304dbb15226SJiaxun Yang if (parent_irq[i] <= 0)
305dbb15226SJiaxun Yang continue;
306dbb15226SJiaxun Yang
307dbb15226SJiaxun Yang priv->handler[i].priv = priv;
308dbb15226SJiaxun Yang irq_set_chained_handler_and_data(parent_irq[i],
309dbb15226SJiaxun Yang liointc_chained_handle_irq, &priv->handler[i]);
310dbb15226SJiaxun Yang }
311dbb15226SJiaxun Yang
3120858ed03SHuacai Chen liointc_handle = domain_handle;
313dbb15226SJiaxun Yang return 0;
314dbb15226SJiaxun Yang
315dbb15226SJiaxun Yang out_free_domain:
316dbb15226SJiaxun Yang irq_domain_remove(domain);
3170858ed03SHuacai Chen out_iounmap:
318dbb15226SJiaxun Yang iounmap(base);
319dbb15226SJiaxun Yang out_free_priv:
320dbb15226SJiaxun Yang kfree(priv);
321dbb15226SJiaxun Yang
3220858ed03SHuacai Chen return -EINVAL;
3230858ed03SHuacai Chen }
3240858ed03SHuacai Chen
3250858ed03SHuacai Chen #ifdef CONFIG_OF
3260858ed03SHuacai Chen
liointc_of_init(struct device_node * node,struct device_node * parent)3270858ed03SHuacai Chen static int __init liointc_of_init(struct device_node *node,
3280858ed03SHuacai Chen struct device_node *parent)
3290858ed03SHuacai Chen {
3300858ed03SHuacai Chen bool have_parent = FALSE;
3310858ed03SHuacai Chen int sz, i, index, revision, err = 0;
3320858ed03SHuacai Chen struct resource res;
3330858ed03SHuacai Chen
3340858ed03SHuacai Chen if (!of_device_is_compatible(node, "loongson,liointc-2.0")) {
3350858ed03SHuacai Chen index = 0;
3360858ed03SHuacai Chen revision = 1;
3370858ed03SHuacai Chen } else {
3380858ed03SHuacai Chen index = of_property_match_string(node, "reg-names", "main");
3390858ed03SHuacai Chen revision = 2;
3400858ed03SHuacai Chen }
3410858ed03SHuacai Chen
3420858ed03SHuacai Chen if (of_address_to_resource(node, index, &res))
3430858ed03SHuacai Chen return -EINVAL;
3440858ed03SHuacai Chen
3450858ed03SHuacai Chen for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
3460858ed03SHuacai Chen parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
3470858ed03SHuacai Chen if (parent_irq[i] > 0)
3480858ed03SHuacai Chen have_parent = TRUE;
3490858ed03SHuacai Chen }
3500858ed03SHuacai Chen if (!have_parent)
3510858ed03SHuacai Chen return -ENODEV;
3520858ed03SHuacai Chen
3530858ed03SHuacai Chen sz = of_property_read_variable_u32_array(node,
3540858ed03SHuacai Chen "loongson,parent_int_map",
3550858ed03SHuacai Chen &parent_int_map[0],
3560858ed03SHuacai Chen LIOINTC_NUM_PARENT,
3570858ed03SHuacai Chen LIOINTC_NUM_PARENT);
3580858ed03SHuacai Chen if (sz < 4) {
3590858ed03SHuacai Chen pr_err("loongson-liointc: No parent_int_map\n");
3600858ed03SHuacai Chen return -ENODEV;
3610858ed03SHuacai Chen }
3620858ed03SHuacai Chen
3630858ed03SHuacai Chen err = liointc_init(res.start, resource_size(&res),
3640858ed03SHuacai Chen revision, of_node_to_fwnode(node), node);
3650858ed03SHuacai Chen if (err < 0)
366dbb15226SJiaxun Yang return err;
3670858ed03SHuacai Chen
3680858ed03SHuacai Chen return 0;
369dbb15226SJiaxun Yang }
370dbb15226SJiaxun Yang
371dbb15226SJiaxun Yang IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
372dbb15226SJiaxun Yang IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
373b2c4c396SQing Zhang IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
3740858ed03SHuacai Chen
3750858ed03SHuacai Chen #endif
3760858ed03SHuacai Chen
3770858ed03SHuacai Chen #ifdef CONFIG_ACPI
htintc_parse_madt(union acpi_subtable_headers * header,const unsigned long end)37870f7b6c0SHuacai Chen static int __init htintc_parse_madt(union acpi_subtable_headers *header,
37970f7b6c0SHuacai Chen const unsigned long end)
38070f7b6c0SHuacai Chen {
38170f7b6c0SHuacai Chen struct acpi_madt_ht_pic *htintc_entry = (struct acpi_madt_ht_pic *)header;
38270f7b6c0SHuacai Chen struct irq_domain *parent = irq_find_matching_fwnode(liointc_handle, DOMAIN_BUS_ANY);
38370f7b6c0SHuacai Chen
38470f7b6c0SHuacai Chen return htvec_acpi_init(parent, htintc_entry);
38570f7b6c0SHuacai Chen }
38670f7b6c0SHuacai Chen
acpi_cascade_irqdomain_init(void)38770f7b6c0SHuacai Chen static int __init acpi_cascade_irqdomain_init(void)
38870f7b6c0SHuacai Chen {
38970f7b6c0SHuacai Chen int r;
39070f7b6c0SHuacai Chen
39170f7b6c0SHuacai Chen r = acpi_table_parse_madt(ACPI_MADT_TYPE_HT_PIC, htintc_parse_madt, 0);
39270f7b6c0SHuacai Chen if (r < 0)
39370f7b6c0SHuacai Chen return r;
39470f7b6c0SHuacai Chen
39570f7b6c0SHuacai Chen return 0;
39670f7b6c0SHuacai Chen }
39770f7b6c0SHuacai Chen
liointc_acpi_init(struct irq_domain * parent,struct acpi_madt_lio_pic * acpi_liointc)3980858ed03SHuacai Chen int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_lio_pic *acpi_liointc)
3990858ed03SHuacai Chen {
4000858ed03SHuacai Chen int ret;
4010858ed03SHuacai Chen struct fwnode_handle *domain_handle;
4020858ed03SHuacai Chen
4030858ed03SHuacai Chen parent_int_map[0] = acpi_liointc->cascade_map[0];
4040858ed03SHuacai Chen parent_int_map[1] = acpi_liointc->cascade_map[1];
4050858ed03SHuacai Chen
4060858ed03SHuacai Chen parent_irq[0] = irq_create_mapping(parent, acpi_liointc->cascade[0]);
4070858ed03SHuacai Chen parent_irq[1] = irq_create_mapping(parent, acpi_liointc->cascade[1]);
4080858ed03SHuacai Chen
4097e4fd7a1SMarc Zyngier domain_handle = irq_domain_alloc_fwnode(&acpi_liointc->address);
4100858ed03SHuacai Chen if (!domain_handle) {
4110858ed03SHuacai Chen pr_err("Unable to allocate domain handle\n");
4120858ed03SHuacai Chen return -ENOMEM;
4130858ed03SHuacai Chen }
41470f7b6c0SHuacai Chen
4150858ed03SHuacai Chen ret = liointc_init(acpi_liointc->address, acpi_liointc->size,
4160858ed03SHuacai Chen 1, domain_handle, NULL);
41770f7b6c0SHuacai Chen if (ret == 0)
41870f7b6c0SHuacai Chen ret = acpi_cascade_irqdomain_init();
41970f7b6c0SHuacai Chen else
4200858ed03SHuacai Chen irq_domain_free_fwnode(domain_handle);
4210858ed03SHuacai Chen
4220858ed03SHuacai Chen return ret;
4230858ed03SHuacai Chen }
4240858ed03SHuacai Chen #endif
425