| /openbmc/linux/Documentation/devicetree/bindings/display/ |
| H A D | xylon,logicvc-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
25 In version 3 of the controller, each layer has fixed memory offset and address
26 starting from the video memory base address for its framebuffer. In version 4,
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| /openbmc/qemu/tests/qemu-iotests/ |
| H A D | 198.out | 2 == create base ==
3 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=16777216
5 == writing whole image base ==
6 wrote 16777216/16777216 bytes at offset 0
9 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=16777216 backing_file=TEST_DIR/t.IMGFMT.base backin…
11 == writing whole image layer ==
12 wrote 16777216/16777216 bytes at offset 0
15 == verify pattern base ==
16 read 16777216/16777216 bytes at offset 0
19 == verify pattern layer ==
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| H A D | 020 | 33 _rm_test_img "$TEST_IMG.base"
36 _rm_test_img "$TEST_DIR/subdir/t.$IMGFMT.base"
59 TEST_IMG="$TEST_IMG.base"
63 echo "Filling base image"
66 for offset in $TEST_OFFSETS; do
68 io writev $(( offset )) 512 1024 64
71 io writev $(( offset + 64 * 1024)) 65536 65536 1
79 _make_test_img -b "$TEST_IMG.base" -F $IMGFMT 6G
84 for offset in $TEST_OFFSETS; do
86 io writev $(( offset + 512 )) 512 1024 64
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| /openbmc/linux/drivers/gpu/drm/atmel-hlcdc/ |
| H A D | atmel_hlcdc_plane.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 #include <linux/mfd/atmel-hlcdc.h>
23 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
25 * @base: DRM plane state
47 struct drm_plane_state base; member
78 return container_of(s, struct atmel_hlcdc_plane_state, base); in drm_plane_state_to_atmel_hlcdc_plane_state()
189 return -ENOTSUPP; in atmel_hlcdc_format_to_plane_mode()
264 factor = (256 * ((8 * (srcsize - 1)) - phidef)) / (dstsize - 1); in atmel_hlcdc_plane_phiscaler_get_factor()
265 max_memsize = ((factor * (dstsize - 1)) + (256 * phidef)) / 2048; in atmel_hlcdc_plane_phiscaler_get_factor()
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| H A D | atmel_hlcdc_dc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
94 #define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
115 #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
132 * Atmel HLCDC Layer registers layout structure
134 * Each HLCDC layer has its own register organization and a given register
137 * This structure stores common registers layout for a given layer and is
138 * used by HLCDC layer code to choose the appropriate register to write to
153 * @general_config: general layer config register
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| /openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_catalog.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
52 * SSPP sub-blocks/features
59 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
60 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
62 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
94 * MIXER sub-blocks/features
95 * @DPU_MIXER_LAYER Layer mixer layer blend configuration,
96 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
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| /openbmc/linux/drivers/gpu/drm/sun4i/ |
| H A D | sun8i_ui_scaler.c | 5 * Copyright (C) 2014-2015 Allwinner
94 int vi_num = mixer->cfg->vi_num; in sun8i_ui_scaler_base()
96 if (mixer->cfg->is_de3) in sun8i_ui_scaler_base()
99 DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num); in sun8i_ui_scaler_base()
103 DE2_UI_SCALER_UNIT_SIZE * (channel - vi_num); in sun8i_ui_scaler_base()
110 scale = step >> (SUN8I_UI_SCALER_SCALE_FRAC - 3); in sun8i_ui_scaler_coef_index()
130 void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) in sun8i_ui_scaler_enable() argument
132 u32 val, base; in sun8i_ui_scaler_enable() local
134 if (WARN_ON(layer < mixer->cfg->vi_num)) in sun8i_ui_scaler_enable()
137 base = sun8i_ui_scaler_base(mixer, layer); in sun8i_ui_scaler_enable()
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| /openbmc/linux/drivers/gpu/drm/arm/ |
| H A D | malidp_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
25 /* Mali DP layer IDs */
43 u8 layer; /* bitmask of layers supporting it */ member
52 * base register offsets
62 u16 id; /* layer ID */
63 u16 base; /* address offset for the register bank */ member
64 u16 ptr; /* address offset for the pointer register */
65 u16 stride_offset; /* offset to the first stride register. */
66 s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
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| /openbmc/linux/drivers/gpu/drm/logicvc/ |
| H A D | logicvc_layer.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
86 struct drm_device *drm_dev = drm_plane->dev; in logicvc_plane_atomic_check()
87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
96 if (!new_state->crtc) in logicvc_plane_atomic_check()
99 crtc_state = drm_atomic_get_existing_crtc_state(new_state->state, in logicvc_plane_atomic_check()
100 new_state->crtc); in logicvc_plane_atomic_check()
102 return -EINVAL; in logicvc_plane_atomic_check()
104 if (new_state->crtc_x < 0 || new_state->crtc_y < 0) { in logicvc_plane_atomic_check()
106 "Negative on-CRTC positions are not supported.\n"); in logicvc_plane_atomic_check()
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| H A D | logicvc_of.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
33 { "layer", LOGICVC_LAYER_ALPHA_LAYER },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
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| /openbmc/linux/drivers/gpu/drm/sprd/ |
| H A D | sprd_dpu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
23 /* DPU Layer registers offset */
35 * @base: DPU controller base address
46 void __iomem *base; member
64 struct drm_crtc base; member
71 return container_of(crtc, struct sprd_dpu, base); in to_sprd_crtc()
75 dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits) in dpu_reg_set() argument
77 u32 bits = readl_relaxed(ctx->base + offset); in dpu_reg_set()
79 writel(bits | set_bits, ctx->base + offset); in dpu_reg_set()
83 dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits) in dpu_reg_clr() argument
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| /openbmc/docs/designs/ |
| H A D | binarystore-via-blobs.md | 5 Created: 2018-12-07
15 - The FRU data may be programmed by MFG and treated as read-only
16 - The FRU data may not be in IPMI FRU format
17 - The data to store may not fit in the data types defined in IPMI FRU spec
18 - Host may want to store multiple copies in e.g. BMC EEPROM
21 simple purpose: provide a read/write/serialize abstraction layer through IPMI
22 blobs transport layer to allow users to store binary data on persistent
27 - It is not a host/BMC mailbox. In general, BMC should reserve the space for
30 - It is not a key store. Because the data stored is accessible to IPMI users and
33 - The data to be stored should not be too large. Since each IPMI packet is
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| /openbmc/linux/drivers/gpu/drm/vmwgfx/ |
| H A D | vmw_surface_cache.h | 3 * SPDX-License-Identifier: GPL-2.0 OR MIT
37 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; in clamped_umul32()
41 * vmw_surface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
54 * vmw_surface_get_mip_size - Given a base level size and the mip level,
74 block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width, in vmw_surface_get_size_in_blocks()
75 desc->blockSize.width); in vmw_surface_get_size_in_blocks()
76 block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height, in vmw_surface_get_size_in_blocks()
77 desc->blockSize.height); in vmw_surface_get_size_in_blocks()
78 block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth, in vmw_surface_get_size_in_blocks()
79 desc->blockSize.depth); in vmw_surface_get_size_in_blocks()
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| /openbmc/linux/drivers/usb/mtu3/ |
| H A D | mtu3.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mtu3.h - MediaTek USB3 DRD header
35 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
36 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
37 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
39 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
40 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
41 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
43 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
44 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
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| /openbmc/linux/drivers/usb/dwc3/ |
| H A D | dwc3-keystone.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-keystone.c - Keystone Specific Glue layer
5 * Copyright (C) 2010-2013 Texas Instruments Incorporated - https://www.ti.com
7 * Author: WingMan Kwok <w-kwok2@ti.com>
14 #include <linux/dma-mapping.h>
42 static inline u32 kdwc3_readl(void __iomem *base, u32 offset) in kdwc3_readl() argument
44 return readl(base + offset); in kdwc3_readl()
47 static inline void kdwc3_writel(void __iomem *base, u32 offset, u32 value) in kdwc3_writel() argument
49 writel(value, base + offset); in kdwc3_writel()
56 val = kdwc3_readl(kdwc->usbss, USBSS_IRQENABLE_SET_0); in kdwc3_enable_irqs()
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| /openbmc/linux/drivers/net/ethernet/freescale/fman/ |
| H A D | fman.h | 1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
21 /* TX-Port: Unsupported Format */
29 /* IPR non-consistent-sp */
66 /* non Frame-Manager error */
117 __be16 l2r; /* Layer 2 result */
118 __be16 l3r; /* Layer 3 result */
119 u8 l4r; /* Layer 4 result */
122 __be16 cksum; /* Running-sum */
123 /* Flags&fragment-offset field of the last IP-header */
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| /openbmc/linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_framebuffer.c | 1 // SPDX-License-Identifier: GPL-2.0
21 for (i = 0; i < fb->format->num_planes; i++) in komeda_fb_destroy()
22 drm_gem_object_put(fb->obj[i]); in komeda_fb_destroy()
31 return drm_gem_handle_create(file, fb->obj[0], handle); in komeda_fb_create_handle()
43 struct drm_framebuffer *fb = &kfb->base; in komeda_fb_afbc_size_check()
44 const struct drm_format_info *info = fb->format; in komeda_fb_afbc_size_check()
49 obj = drm_gem_object_lookup(file, mode_cmd->handles[0]); in komeda_fb_afbc_size_check()
52 return -ENOENT; in komeda_fb_afbc_size_check()
55 switch (fb->modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK) { in komeda_fb_afbc_size_check()
66 fb->modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK); in komeda_fb_afbc_size_check()
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| /openbmc/u-boot/drivers/video/ |
| H A D | mali_dp.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016-2018 ARM Ltd.
35 /* offsets inside the layer register block */
97 u8 clear_irq; /* offset for IRQ clear register */
108 * reading from the old CORE_ID offset will always in malidp_get_hwid()
114 /* otherwise try the other gen CORE_ID offset */ in malidp_get_hwid()
127 while (tries--) { in malidp_wait_configdone()
128 status = readl(malidp->dc_status_addr); in malidp_wait_configdone()
129 if ((status >> malidp->config_bit_shift) & 1) in malidp_wait_configdone()
135 return -ETIMEDOUT; in malidp_wait_configdone()
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| /openbmc/u-boot/drivers/usb/dwc3/ |
| H A D | dwc3-omap.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-omap.c - OMAP Specific Glue layer
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported
13 * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
20 #include <dwc3-omap-uboot.h>
21 #include <linux/usb/dwc3-omap.h>
27 #include "linux-compat.h"
122 void __iomem *base; member
138 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) in dwc3_omap_readl() argument
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | ti,cal.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL)
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
13 The Camera Adaptation Layer (CAL) is a key component for image capture
15 processing capability to connect CSI2 image-sensor modules to the
24 - ti,dra72-cal
26 - ti,dra72-pre-es2-cal
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| /openbmc/linux/drivers/media/platform/ti/cal/ |
| H A D | cal.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TI Camera Access Layer (CAL)
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
22 #include <media/media-device.h>
23 #include <media/v4l2-async.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-dev.h>
26 #include <media/v4l2-device.h>
27 #include <media/v4l2-fwnode.h>
28 #include <media/v4l2-subdev.h>
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| /openbmc/linux/include/misc/ |
| H A D | ocxl.h | 1 // SPDX-License-Identifier: GPL-2.0+
14 * reuse common code. A bit like a in-kernel library.
22 int dvsec_afu_control_pos; /* offset of AFU control DVSEC */
32 u8 pp_mmio_bar; /* per-process MMIO area */
44 int dvsec_tl_pos; /* offset of the Transaction Layer DVSEC */
45 int dvsec_function_pos; /* offset of the Function DVSEC */
46 int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */
52 OCXL_BIG_ENDIAN = 0, /**< AFU data is big-endian */
53 OCXL_LITTLE_ENDIAN = 1, /**< AFU data is little-endian */
65 * ocxl_function_open() - Open an OpenCAPI function on an OpenCAPI device
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| /openbmc/qemu/tests/qemu-iotests/tests/ |
| H A D | qemu-img-bitmaps.out | 1 QA output created by qemu-img-bitmaps
5 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=10485760
6 wrote 1048576/1048576 bytes at offset 3145728
8 Formatting 'TEST_DIR/t.IMGFMT.orig', fmt=IMGFMT size=10485760 backing_file=TEST_DIR/t.IMGFMT.base b…
9 wrote 1048576/1048576 bytes at offset 0
11 wrote 1048576/1048576 bytes at offset 3145728
13 wrote 1048576/1048576 bytes at offset 1048576
15 wrote 1048576/1048576 bytes at offset 2097152
18 === Bitmap preservation not possible to non-qcow2 ===
20 qemu-img: Format driver 'raw' does not support bitmaps
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| /openbmc/linux/drivers/irqchip/ |
| H A D | spear-shirq.c | 2 * SPEAr platform shared irq layer source file
4 * Copyright (C) 2009-2012 ST Microelectronics
31 * base: Base register address
32 * status_reg: Status register offset for chained interrupt handler
33 * mask_reg: Mask register offset for irq chip
35 * virq_base: Base virtual interrupt number
37 * offset: Bit offset of the first interrupt
42 void __iomem *base; member
48 u32 offset; member
61 u32 val, shift = d->irq - shirq->virq_base + shirq->offset; in shirq_irq_mask()
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| /openbmc/linux/net/netfilter/ |
| H A D | nft_payload.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2009 Patrick McHardy <kaber@trash.net>
19 /* For layer 4 checksum field offset. */
34 veth->h_vlan_proto = skb->vlan_proto; in nft_payload_rebuild_vlan_hdr()
35 veth->h_vlan_TCI = htons(skb_vlan_tag_get(skb)); in nft_payload_rebuild_vlan_hdr()
36 veth->h_vlan_encapsulated_proto = skb->protocol; in nft_payload_rebuild_vlan_hdr()
43 nft_payload_copy_vlan(u32 *d, const struct sk_buff *skb, u8 offset, u8 len) in nft_payload_copy_vlan() argument
45 int mac_off = skb_mac_header(skb) - skb->data; in nft_payload_copy_vlan()
50 if (offset < VLAN_ETH_HLEN) { in nft_payload_copy_vlan()
56 if (offset + len > VLAN_ETH_HLEN) in nft_payload_copy_vlan()
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