1e559355aSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2ad49f860SLiviu Dudau /*
3ad49f860SLiviu Dudau *
4ad49f860SLiviu Dudau * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
5ad49f860SLiviu Dudau *
6ad49f860SLiviu Dudau * ARM Mali DP hardware manipulation routines.
7ad49f860SLiviu Dudau */
8ad49f860SLiviu Dudau
9ad49f860SLiviu Dudau #ifndef __MALIDP_HW_H__
10ad49f860SLiviu Dudau #define __MALIDP_HW_H__
11ad49f860SLiviu Dudau
12ad49f860SLiviu Dudau #include <linux/bitops.h>
13ad49f860SLiviu Dudau #include "malidp_regs.h"
14ad49f860SLiviu Dudau
15ad49f860SLiviu Dudau struct videomode;
16ad49f860SLiviu Dudau struct clk;
17ad49f860SLiviu Dudau
18ad49f860SLiviu Dudau /* Mali DP IP blocks */
19ad49f860SLiviu Dudau enum {
20ad49f860SLiviu Dudau MALIDP_DE_BLOCK = 0,
21ad49f860SLiviu Dudau MALIDP_SE_BLOCK,
22ad49f860SLiviu Dudau MALIDP_DC_BLOCK
23ad49f860SLiviu Dudau };
24ad49f860SLiviu Dudau
25ad49f860SLiviu Dudau /* Mali DP layer IDs */
26ad49f860SLiviu Dudau enum {
27ad49f860SLiviu Dudau DE_VIDEO1 = BIT(0),
28ad49f860SLiviu Dudau DE_GRAPHICS1 = BIT(1),
29ad49f860SLiviu Dudau DE_GRAPHICS2 = BIT(2), /* used only in DP500 */
30ad49f860SLiviu Dudau DE_VIDEO2 = BIT(3),
31ad49f860SLiviu Dudau DE_SMART = BIT(4),
32a67bbbe2SBrian Starkey SE_MEMWRITE = BIT(5),
33ad49f860SLiviu Dudau };
34ad49f860SLiviu Dudau
3566da13a5SLiviu Dudau enum rotation_features {
3666da13a5SLiviu Dudau ROTATE_NONE, /* does not support rotation at all */
3766da13a5SLiviu Dudau ROTATE_ANY, /* supports rotation on any buffers */
3866da13a5SLiviu Dudau ROTATE_COMPRESSED, /* supports rotation only on compressed buffers */
3966da13a5SLiviu Dudau };
4066da13a5SLiviu Dudau
416211b486SBrian Starkey struct malidp_format_id {
42ad49f860SLiviu Dudau u32 format; /* DRM fourcc */
43ad49f860SLiviu Dudau u8 layer; /* bitmask of layers supporting it */
44ad49f860SLiviu Dudau u8 id; /* used internally */
45ad49f860SLiviu Dudau };
46ad49f860SLiviu Dudau
47ad49f860SLiviu Dudau #define MALIDP_INVALID_FORMAT_ID 0xff
48ad49f860SLiviu Dudau
49ad49f860SLiviu Dudau /*
50ad49f860SLiviu Dudau * hide the differences between register maps
51ad49f860SLiviu Dudau * by using a common structure to hold the
52ad49f860SLiviu Dudau * base register offsets
53ad49f860SLiviu Dudau */
54ad49f860SLiviu Dudau
55ad49f860SLiviu Dudau struct malidp_irq_map {
56ad49f860SLiviu Dudau u32 irq_mask; /* mask of IRQs that can be enabled in the block */
57ad49f860SLiviu Dudau u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */
58613c5c7fSAlexandru Gheorghe u32 err_mask; /* mask of bits that represent errors */
59ad49f860SLiviu Dudau };
60ad49f860SLiviu Dudau
61ad49f860SLiviu Dudau struct malidp_layer {
62ad49f860SLiviu Dudau u16 id; /* layer ID */
63ad49f860SLiviu Dudau u16 base; /* address offset for the register bank */
64ad49f860SLiviu Dudau u16 ptr; /* address offset for the pointer register */
656e810eb5SMihail Atanassov u16 stride_offset; /* offset to the first stride register. */
666e810eb5SMihail Atanassov s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
671f23a56aSJamie Fox u16 mmu_ctrl_offset; /* offset to the MMU control register */
6866da13a5SLiviu Dudau enum rotation_features rot; /* type of rotation supported */
6954b4260aSAyan Kumar Halder /* address offset for the AFBC decoder registers */
7054b4260aSAyan Kumar Halder u16 afbc_decoder_offset;
71ad49f860SLiviu Dudau };
72ad49f860SLiviu Dudau
7328ce675bSMihail Atanassov enum malidp_scaling_coeff_set {
7428ce675bSMihail Atanassov MALIDP_UPSCALING_COEFFS = 1,
7528ce675bSMihail Atanassov MALIDP_DOWNSCALING_1_5_COEFFS = 2,
7628ce675bSMihail Atanassov MALIDP_DOWNSCALING_2_COEFFS = 3,
7728ce675bSMihail Atanassov MALIDP_DOWNSCALING_2_75_COEFFS = 4,
7828ce675bSMihail Atanassov MALIDP_DOWNSCALING_4_COEFFS = 5,
7928ce675bSMihail Atanassov };
8028ce675bSMihail Atanassov
8128ce675bSMihail Atanassov struct malidp_se_config {
8228ce675bSMihail Atanassov u8 scale_enable : 1;
830274e6a0SMihail Atanassov u8 enhancer_enable : 1;
8428ce675bSMihail Atanassov u8 hcoeff : 3;
8528ce675bSMihail Atanassov u8 vcoeff : 3;
8628ce675bSMihail Atanassov u8 plane_src_id;
8728ce675bSMihail Atanassov u16 input_w, input_h;
8828ce675bSMihail Atanassov u16 output_w, output_h;
8928ce675bSMihail Atanassov u32 h_init_phase, h_delta_phase;
9028ce675bSMihail Atanassov u32 v_init_phase, v_delta_phase;
9128ce675bSMihail Atanassov };
9228ce675bSMihail Atanassov
93ad49f860SLiviu Dudau /* regmap features */
945e290226SAyan Kumar Halder #define MALIDP_REGMAP_HAS_CLEARIRQ BIT(0)
955e290226SAyan Kumar Halder #define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT BIT(1)
965e290226SAyan Kumar Halder #define MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT BIT(2)
975e290226SAyan Kumar Halder #define MALIDP_DEVICE_AFBC_YUYV_USE_422_P2 BIT(3)
98ad49f860SLiviu Dudau
99ad49f860SLiviu Dudau struct malidp_hw_regmap {
100ad49f860SLiviu Dudau /* address offset of the DE register bank */
101ad49f860SLiviu Dudau /* is always 0x0000 */
10202725d31SMihail Atanassov /* address offset of the DE coefficients registers */
10302725d31SMihail Atanassov const u16 coeffs_base;
104ad49f860SLiviu Dudau /* address offset of the SE registers bank */
105ad49f860SLiviu Dudau const u16 se_base;
106ad49f860SLiviu Dudau /* address offset of the DC registers bank */
107ad49f860SLiviu Dudau const u16 dc_base;
108ad49f860SLiviu Dudau
109ad49f860SLiviu Dudau /* address offset for the output depth register */
110ad49f860SLiviu Dudau const u16 out_depth_base;
111ad49f860SLiviu Dudau
112ad49f860SLiviu Dudau /* bitmap with register map features */
113ad49f860SLiviu Dudau const u8 features;
114ad49f860SLiviu Dudau
115ad49f860SLiviu Dudau /* list of supported layers */
116ad49f860SLiviu Dudau const u8 n_layers;
117ad49f860SLiviu Dudau const struct malidp_layer *layers;
118ad49f860SLiviu Dudau
119ad49f860SLiviu Dudau const struct malidp_irq_map de_irq_map;
120ad49f860SLiviu Dudau const struct malidp_irq_map se_irq_map;
121ad49f860SLiviu Dudau const struct malidp_irq_map dc_irq_map;
122ad49f860SLiviu Dudau
1236211b486SBrian Starkey /* list of supported pixel formats for each layer */
1246211b486SBrian Starkey const struct malidp_format_id *pixel_formats;
1256211b486SBrian Starkey const u8 n_pixel_formats;
126a228062cSBrian Starkey
127a228062cSBrian Starkey /* pitch alignment requirement in bytes */
128a228062cSBrian Starkey const u8 bus_align_bytes;
129ad49f860SLiviu Dudau };
130ad49f860SLiviu Dudau
13183d642eeSMihail Atanassov /* device features */
13283d642eeSMihail Atanassov /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */
13383d642eeSMihail Atanassov #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0)
13483d642eeSMihail Atanassov
135a6993b21SLiviu Dudau struct malidp_hw_device;
136ad49f860SLiviu Dudau
137a6993b21SLiviu Dudau /*
138a6993b21SLiviu Dudau * Static structure containing hardware specific data and pointers to
139a6993b21SLiviu Dudau * functions that behave differently between various versions of the IP.
140a6993b21SLiviu Dudau */
141a6993b21SLiviu Dudau struct malidp_hw {
142a6993b21SLiviu Dudau const struct malidp_hw_regmap map;
143ad49f860SLiviu Dudau
144ad49f860SLiviu Dudau /*
145ad49f860SLiviu Dudau * Validate the driver instance against the hardware bits
146ad49f860SLiviu Dudau */
147ad49f860SLiviu Dudau int (*query_hw)(struct malidp_hw_device *hwdev);
148ad49f860SLiviu Dudau
149ad49f860SLiviu Dudau /*
150ad49f860SLiviu Dudau * Set the hardware into config mode, ready to accept mode changes
151ad49f860SLiviu Dudau */
152ad49f860SLiviu Dudau void (*enter_config_mode)(struct malidp_hw_device *hwdev);
153ad49f860SLiviu Dudau
154ad49f860SLiviu Dudau /*
155ad49f860SLiviu Dudau * Tell hardware to exit configuration mode
156ad49f860SLiviu Dudau */
157ad49f860SLiviu Dudau void (*leave_config_mode)(struct malidp_hw_device *hwdev);
158ad49f860SLiviu Dudau
159ad49f860SLiviu Dudau /*
160ad49f860SLiviu Dudau * Query if hardware is in configuration mode
161ad49f860SLiviu Dudau */
162ad49f860SLiviu Dudau bool (*in_config_mode)(struct malidp_hw_device *hwdev);
163ad49f860SLiviu Dudau
164ad49f860SLiviu Dudau /*
1650735cfdfSLiviu Dudau * Set/clear configuration valid flag for hardware parameters that can
1660735cfdfSLiviu Dudau * be changed outside the configuration mode to the given value.
1670735cfdfSLiviu Dudau * Hardware will use the new settings when config valid is set,
1680735cfdfSLiviu Dudau * after the end of the current buffer scanout, and will ignore
1690735cfdfSLiviu Dudau * any new values for those parameters if config valid flag is cleared
170ad49f860SLiviu Dudau */
1710735cfdfSLiviu Dudau void (*set_config_valid)(struct malidp_hw_device *hwdev, u8 value);
172ad49f860SLiviu Dudau
173ad49f860SLiviu Dudau /*
174ad49f860SLiviu Dudau * Set a new mode in hardware. Requires the hardware to be in
175ad49f860SLiviu Dudau * configuration mode before this function is called.
176ad49f860SLiviu Dudau */
177ad49f860SLiviu Dudau void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m);
178ad49f860SLiviu Dudau
179ad49f860SLiviu Dudau /*
180ad49f860SLiviu Dudau * Calculate the required rotation memory given the active area
181ad49f860SLiviu Dudau * and the buffer format.
182ad49f860SLiviu Dudau */
183b8207562SAyan Kumar Halder int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h,
184b8207562SAyan Kumar Halder u32 fmt, bool has_modifier);
185ad49f860SLiviu Dudau
18628ce675bSMihail Atanassov int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev,
18728ce675bSMihail Atanassov struct malidp_se_config *se_config,
18828ce675bSMihail Atanassov struct malidp_se_config *old_config);
18928ce675bSMihail Atanassov
190c2e7f82dSMihail Atanassov long (*se_calc_mclk)(struct malidp_hw_device *hwdev,
191c2e7f82dSMihail Atanassov struct malidp_se_config *se_config,
192c2e7f82dSMihail Atanassov struct videomode *vm);
1931cb3cbe7SLiviu Dudau /*
194846c87a0SLiviu Dudau * Enable writing to memory the content of the next frame
195846c87a0SLiviu Dudau * @param hwdev - malidp_hw_device structure containing the HW description
196846c87a0SLiviu Dudau * @param addrs - array of addresses for each plane
197846c87a0SLiviu Dudau * @param pitches - array of pitches for each plane
198846c87a0SLiviu Dudau * @param num_planes - number of planes to be written
199846c87a0SLiviu Dudau * @param w - width of the output frame
200846c87a0SLiviu Dudau * @param h - height of the output frame
201846c87a0SLiviu Dudau * @param fmt_id - internal format ID of output buffer
202846c87a0SLiviu Dudau */
203846c87a0SLiviu Dudau int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs,
204b1150781SAlexandru Gheorghe s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id,
205b1150781SAlexandru Gheorghe const s16 *rgb2yuv_coeffs);
206846c87a0SLiviu Dudau
207846c87a0SLiviu Dudau /*
208846c87a0SLiviu Dudau * Disable the writing to memory of the next frame's content.
209846c87a0SLiviu Dudau */
210846c87a0SLiviu Dudau void (*disable_memwrite)(struct malidp_hw_device *hwdev);
211c2e7f82dSMihail Atanassov
212ad49f860SLiviu Dudau u8 features;
213ad49f860SLiviu Dudau };
214ad49f860SLiviu Dudau
215ad49f860SLiviu Dudau /* Supported variants of the hardware */
216ad49f860SLiviu Dudau enum {
217ad49f860SLiviu Dudau MALIDP_500 = 0,
218ad49f860SLiviu Dudau MALIDP_550,
219ad49f860SLiviu Dudau MALIDP_650,
220ad49f860SLiviu Dudau /* keep the next entry last */
221ad49f860SLiviu Dudau MALIDP_MAX_DEVICES
222ad49f860SLiviu Dudau };
223ad49f860SLiviu Dudau
224a6993b21SLiviu Dudau extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES];
225a6993b21SLiviu Dudau
226a6993b21SLiviu Dudau /*
227a6993b21SLiviu Dudau * Structure used by the driver during runtime operation.
228a6993b21SLiviu Dudau */
229a6993b21SLiviu Dudau struct malidp_hw_device {
230a6993b21SLiviu Dudau struct malidp_hw *hw;
231a6993b21SLiviu Dudau void __iomem *regs;
232a6993b21SLiviu Dudau
233a6993b21SLiviu Dudau /* APB clock */
234a6993b21SLiviu Dudau struct clk *pclk;
235a6993b21SLiviu Dudau /* AXI clock */
236a6993b21SLiviu Dudau struct clk *aclk;
237a6993b21SLiviu Dudau /* main clock for display core */
238a6993b21SLiviu Dudau struct clk *mclk;
239a6993b21SLiviu Dudau /* pixel clock for display core */
240a6993b21SLiviu Dudau struct clk *pxlclk;
241a6993b21SLiviu Dudau
242a6993b21SLiviu Dudau u8 min_line_size;
243a6993b21SLiviu Dudau u16 max_line_size;
244f877006dSAyan Kumar Halder u32 output_color_depth;
245a6993b21SLiviu Dudau
246a6993b21SLiviu Dudau /* track the device PM state */
247a6993b21SLiviu Dudau bool pm_suspended;
248a6993b21SLiviu Dudau
2491cb3cbe7SLiviu Dudau /* track the SE memory writeback state */
2501cb3cbe7SLiviu Dudau u8 mw_state;
2511cb3cbe7SLiviu Dudau
252a6993b21SLiviu Dudau /* size of memory used for rotating layers, up to two banks available */
253a6993b21SLiviu Dudau u32 rotation_memory[2];
254d298e6a2SWen He
255d298e6a2SWen He /* priority level of RQOS register used for driven the ARQOS signal */
256d298e6a2SWen He u32 arqos_value;
257a6993b21SLiviu Dudau };
258ad49f860SLiviu Dudau
malidp_hw_read(struct malidp_hw_device * hwdev,u32 reg)259ad49f860SLiviu Dudau static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
260ad49f860SLiviu Dudau {
26185f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended);
262ad49f860SLiviu Dudau return readl(hwdev->regs + reg);
263ad49f860SLiviu Dudau }
264ad49f860SLiviu Dudau
malidp_hw_write(struct malidp_hw_device * hwdev,u32 value,u32 reg)265ad49f860SLiviu Dudau static inline void malidp_hw_write(struct malidp_hw_device *hwdev,
266ad49f860SLiviu Dudau u32 value, u32 reg)
267ad49f860SLiviu Dudau {
26885f64218SLiviu Dudau WARN_ON(hwdev->pm_suspended);
269ad49f860SLiviu Dudau writel(value, hwdev->regs + reg);
270ad49f860SLiviu Dudau }
271ad49f860SLiviu Dudau
malidp_hw_setbits(struct malidp_hw_device * hwdev,u32 mask,u32 reg)272ad49f860SLiviu Dudau static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev,
273ad49f860SLiviu Dudau u32 mask, u32 reg)
274ad49f860SLiviu Dudau {
275ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg);
276ad49f860SLiviu Dudau
277ad49f860SLiviu Dudau data |= mask;
278ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg);
279ad49f860SLiviu Dudau }
280ad49f860SLiviu Dudau
malidp_hw_clearbits(struct malidp_hw_device * hwdev,u32 mask,u32 reg)281ad49f860SLiviu Dudau static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev,
282ad49f860SLiviu Dudau u32 mask, u32 reg)
283ad49f860SLiviu Dudau {
284ad49f860SLiviu Dudau u32 data = malidp_hw_read(hwdev, reg);
285ad49f860SLiviu Dudau
286ad49f860SLiviu Dudau data &= ~mask;
287ad49f860SLiviu Dudau malidp_hw_write(hwdev, data, reg);
288ad49f860SLiviu Dudau }
289ad49f860SLiviu Dudau
malidp_get_block_base(struct malidp_hw_device * hwdev,u8 block)290ad49f860SLiviu Dudau static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev,
291ad49f860SLiviu Dudau u8 block)
292ad49f860SLiviu Dudau {
293ad49f860SLiviu Dudau switch (block) {
294ad49f860SLiviu Dudau case MALIDP_SE_BLOCK:
295a6993b21SLiviu Dudau return hwdev->hw->map.se_base;
296ad49f860SLiviu Dudau case MALIDP_DC_BLOCK:
297a6993b21SLiviu Dudau return hwdev->hw->map.dc_base;
298ad49f860SLiviu Dudau }
299ad49f860SLiviu Dudau
300ad49f860SLiviu Dudau return 0;
301ad49f860SLiviu Dudau }
302ad49f860SLiviu Dudau
malidp_hw_disable_irq(struct malidp_hw_device * hwdev,u8 block,u32 irq)303ad49f860SLiviu Dudau static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev,
304ad49f860SLiviu Dudau u8 block, u32 irq)
305ad49f860SLiviu Dudau {
306ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block);
307ad49f860SLiviu Dudau
308ad49f860SLiviu Dudau malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
309ad49f860SLiviu Dudau }
310ad49f860SLiviu Dudau
malidp_hw_enable_irq(struct malidp_hw_device * hwdev,u8 block,u32 irq)311ad49f860SLiviu Dudau static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev,
312ad49f860SLiviu Dudau u8 block, u32 irq)
313ad49f860SLiviu Dudau {
314ad49f860SLiviu Dudau u32 base = malidp_get_block_base(hwdev, block);
315ad49f860SLiviu Dudau
316ad49f860SLiviu Dudau malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
317ad49f860SLiviu Dudau }
318ad49f860SLiviu Dudau
319ad49f860SLiviu Dudau int malidp_de_irq_init(struct drm_device *drm, int irq);
320ff8fc26aSAyan Kumar Halder void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev);
321ff8fc26aSAyan Kumar Halder void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev);
32262862cfbSAyan Kumar Halder void malidp_de_irq_fini(struct malidp_hw_device *hwdev);
323ad49f860SLiviu Dudau int malidp_se_irq_init(struct drm_device *drm, int irq);
32462862cfbSAyan Kumar Halder void malidp_se_irq_fini(struct malidp_hw_device *hwdev);
325ad49f860SLiviu Dudau
326ad49f860SLiviu Dudau u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
3275e290226SAyan Kumar Halder u8 layer_id, u32 format, bool has_modifier);
328ad49f860SLiviu Dudau
329b8207562SAyan Kumar Halder int malidp_format_get_bpp(u32 fmt);
330b8207562SAyan Kumar Halder
malidp_hw_get_pitch_align(struct malidp_hw_device * hwdev,bool rotated)331fcad73b9SLiviu Dudau static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated)
332a228062cSBrian Starkey {
333fcad73b9SLiviu Dudau /*
334fcad73b9SLiviu Dudau * only hardware that cannot do 8 bytes bus alignments have further
335fcad73b9SLiviu Dudau * constraints on rotated planes
336fcad73b9SLiviu Dudau */
337fcad73b9SLiviu Dudau if (hwdev->hw->map.bus_align_bytes == 8)
338fcad73b9SLiviu Dudau return 8;
339fcad73b9SLiviu Dudau else
340fcad73b9SLiviu Dudau return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0);
341a228062cSBrian Starkey }
342a228062cSBrian Starkey
34328ce675bSMihail Atanassov /* U16.16 */
34428ce675bSMihail Atanassov #define FP_1_00000 0x00010000 /* 1.0 */
34528ce675bSMihail Atanassov #define FP_0_66667 0x0000AAAA /* 0.6667 = 1/1.5 */
34628ce675bSMihail Atanassov #define FP_0_50000 0x00008000 /* 0.5 = 1/2 */
34728ce675bSMihail Atanassov #define FP_0_36363 0x00005D17 /* 0.36363 = 1/2.75 */
34828ce675bSMihail Atanassov #define FP_0_25000 0x00004000 /* 0.25 = 1/4 */
34928ce675bSMihail Atanassov
35028ce675bSMihail Atanassov static inline enum malidp_scaling_coeff_set
malidp_se_select_coeffs(u32 upscale_factor)35128ce675bSMihail Atanassov malidp_se_select_coeffs(u32 upscale_factor)
35228ce675bSMihail Atanassov {
35328ce675bSMihail Atanassov return (upscale_factor >= FP_1_00000) ? MALIDP_UPSCALING_COEFFS :
35428ce675bSMihail Atanassov (upscale_factor >= FP_0_66667) ? MALIDP_DOWNSCALING_1_5_COEFFS :
35528ce675bSMihail Atanassov (upscale_factor >= FP_0_50000) ? MALIDP_DOWNSCALING_2_COEFFS :
35628ce675bSMihail Atanassov (upscale_factor >= FP_0_36363) ? MALIDP_DOWNSCALING_2_75_COEFFS :
35728ce675bSMihail Atanassov MALIDP_DOWNSCALING_4_COEFFS;
35828ce675bSMihail Atanassov }
35928ce675bSMihail Atanassov
36028ce675bSMihail Atanassov #undef FP_0_25000
36128ce675bSMihail Atanassov #undef FP_0_36363
36228ce675bSMihail Atanassov #undef FP_0_50000
36328ce675bSMihail Atanassov #undef FP_0_66667
36428ce675bSMihail Atanassov #undef FP_1_00000
3650274e6a0SMihail Atanassov
malidp_se_set_enh_coeffs(struct malidp_hw_device * hwdev)3660274e6a0SMihail Atanassov static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev)
3670274e6a0SMihail Atanassov {
3680274e6a0SMihail Atanassov static const s32 enhancer_coeffs[] = {
3690274e6a0SMihail Atanassov -8, -8, -8, -8, 128, -8, -8, -8, -8
3700274e6a0SMihail Atanassov };
3710274e6a0SMihail Atanassov u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) |
3720274e6a0SMihail Atanassov MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL);
373a6993b21SLiviu Dudau u32 image_enh = hwdev->hw->map.se_base +
374a6993b21SLiviu Dudau ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
3750274e6a0SMihail Atanassov 0x10 : 0xC) + MALIDP_SE_IMAGE_ENH;
3760274e6a0SMihail Atanassov u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0;
3770274e6a0SMihail Atanassov int i;
3780274e6a0SMihail Atanassov
3790274e6a0SMihail Atanassov malidp_hw_write(hwdev, val, image_enh);
3800274e6a0SMihail Atanassov for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i)
3810274e6a0SMihail Atanassov malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4);
3820274e6a0SMihail Atanassov }
3830274e6a0SMihail Atanassov
384ad49f860SLiviu Dudau /*
385ad49f860SLiviu Dudau * background color components are defined as 12bits values,
386ad49f860SLiviu Dudau * they will be shifted right when stored on hardware that
387ad49f860SLiviu Dudau * supports only 8bits per channel
388ad49f860SLiviu Dudau */
389ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_R 0x000
390ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_G 0x000
391ad49f860SLiviu Dudau #define MALIDP_BGND_COLOR_B 0x000
392ad49f860SLiviu Dudau
3936954f245SMihail Atanassov #define MALIDP_COLORADJ_NUM_COEFFS 12
39402725d31SMihail Atanassov #define MALIDP_COEFFTAB_NUM_COEFFS 64
39502725d31SMihail Atanassov
39602725d31SMihail Atanassov #define MALIDP_GAMMA_LUT_SIZE 4096
39702725d31SMihail Atanassov
3985e290226SAyan Kumar Halder #define AFBC_SIZE_MASK AFBC_FORMAT_MOD_BLOCK_SIZE_MASK
3995e290226SAyan Kumar Halder #define AFBC_SIZE_16X16 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16
4005e290226SAyan Kumar Halder #define AFBC_YTR AFBC_FORMAT_MOD_YTR
4015e290226SAyan Kumar Halder #define AFBC_SPARSE AFBC_FORMAT_MOD_SPARSE
4025e290226SAyan Kumar Halder #define AFBC_CBR AFBC_FORMAT_MOD_CBR
4035e290226SAyan Kumar Halder #define AFBC_SPLIT AFBC_FORMAT_MOD_SPLIT
4045e290226SAyan Kumar Halder #define AFBC_TILED AFBC_FORMAT_MOD_TILED
4055e290226SAyan Kumar Halder #define AFBC_SC AFBC_FORMAT_MOD_SC
4065e290226SAyan Kumar Halder
4075e290226SAyan Kumar Halder #define AFBC_MOD_VALID_BITS (AFBC_SIZE_MASK | AFBC_YTR | AFBC_SPLIT | \
4085e290226SAyan Kumar Halder AFBC_SPARSE | AFBC_CBR | AFBC_TILED | AFBC_SC)
4095e290226SAyan Kumar Halder
4105e290226SAyan Kumar Halder extern const u64 malidp_format_modifiers[];
4113dae1c09SAyan Kumar Halder
412ad49f860SLiviu Dudau #endif /* __MALIDP_HW_H__ */
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