/openbmc/u-boot/arch/arm/mach-tegra/ |
H A D | xusb-padctl-common.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt 11 #include "xusb-padctl-common.h" 17 if (phy && phy->ops && phy->ops->prepare) in tegra_xusb_phy_prepare() 18 return phy->ops->prepare(phy); in tegra_xusb_phy_prepare() 20 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_prepare() 25 if (phy && phy->ops && phy->ops->enable) in tegra_xusb_phy_enable() 26 return phy->ops->enable(phy); in tegra_xusb_phy_enable() 28 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_enable() [all …]
|
/openbmc/u-boot/drivers/phy/marvell/ |
H A D | comphy_core.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2015-2016 Marvell International Ltd. 54 u32 lane; in comphy_print() local 56 for (lane = 0; lane < chip_cfg->comphy_lanes_count; in comphy_print() 57 lane++, comphy_map_data++) { in comphy_print() 58 if (comphy_map_data->speed == PHY_SPEED_INVALID) { in comphy_print() 59 printf("Comphy-%d: %-13s\n", lane, in comphy_print() 60 get_type_string(comphy_map_data->type)); in comphy_print() 62 printf("Comphy-%d: %-13s %-10s\n", lane, in comphy_print() 63 get_type_string(comphy_map_data->type), in comphy_print() [all …]
|
/openbmc/linux/drivers/phy/tegra/ |
H A D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. 21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0) 280 writel(value, priv->ao_regs + offset); in ao_writel() 285 return readl(priv->ao_regs + offset); in ao_readl() 304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe() 306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe() 307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe() 308 usb2->base.index = index; in tegra186_usb2_lane_probe() 309 usb2->base.pad = pad; in tegra186_usb2_lane_probe() [all …]
|
H A D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. 31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate() 32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate() 34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate() 35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate() 38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate() 39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate() 45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate() 53 .compatible = "nvidia,tegra124-xusb-padctl", [all …]
|
H A D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only 229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable() 231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable() 251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable() 259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable() 261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable() 264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable() 284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable() 292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local 297 return -ENODEV; in tegra124_usb3_save_context() [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | parade,ps8622.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 15 - parade,ps8622 16 - parade,ps8625 21 lane-count: 26 use-external-pwm: 30 reset-gpios: 34 sleep-gpios: [all …]
|
/openbmc/linux/drivers/gpu/drm/bridge/ |
H A D | cros-ec-anx7688.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * CrOS EC ANX7688 HDMI->DP bridge driver 58 if (!anx->filter) in cros_ec_anx7688_bridge_mode_fixup() 61 /* Read both regs 0x85 (bandwidth) and 0x86 (lane count). */ in cros_ec_anx7688_bridge_mode_fixup() 62 ret = regmap_bulk_read(anx->regmap, ANX7688_DP_BANDWIDTH_REG, regs, 2); in cros_ec_anx7688_bridge_mode_fixup() 64 DRM_ERROR("Failed to read bandwidth/lane count\n"); in cros_ec_anx7688_bridge_mode_fixup() 72 DRM_ERROR("Invalid bandwidth/lane count (%02x/%d)\n", dpbw, in cros_ec_anx7688_bridge_mode_fixup() 81 requiredbw = mode->clock * 8 * 3; in cros_ec_anx7688_bridge_mode_fixup() 87 DRM_ERROR("Bandwidth/lane count are 0, not rejecting modes\n"); in cros_ec_anx7688_bridge_mode_fixup() 100 struct device *dev = &client->dev; in cros_ec_anx7688_bridge_probe() [all …]
|
/openbmc/u-boot/drivers/video/ |
H A D | logicore_dp_tx.c | 1 // SPDX-License-Identifier: GPL-2.0+ 31 /* The maximum pre-emphasis level is 3 */ 42 * enum link_training_states - States for link training state machine 47 * @TS_ADJUST_LANE_COUNT: State where lane count is reduced in reaction to 62 * struct aux_transaction - Description of an AUX channel transaction 76 * struct main_stream_attributes - Main stream attributes 87 * to the native internal 16-bit datapath 150 * struct link_config - Description of link configuration 151 * @lane_count: Currently selected lane count for this link 157 * @max_lane_count: Maximum lane count for this link [all …]
|
/openbmc/linux/Documentation/ABI/testing/ |
H A D | sysfs-devices-platform-kunpeng_hccs | 9 contains read-only attributes exposing some summarization 19 lane (bool). 20 crc_err_cnt: (RO) total CRC err count for all ports on this 32 contains read-only attributes exposing some summarization 43 lane (bool). 44 crc_err_cnt: (RO) total CRC err count for all ports on this 60 contains read-only attributes exposing information about 63 HCCS port belongs. For example, X ranges from to 'n - 1' if the 73 type: (RO) port type (string), e.g. HCCS-v1 -> H32 74 lane_mode: (RO) the lane mode of this port (string), e.g. x8 [all …]
|
/openbmc/linux/drivers/net/ethernet/sfc/falcon/ |
H A D | txc43128_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Copyright 2006-2011 Solarflare Communications Inc. 9 * see www.transwitch.com, part is TXC-43128 30 * Compile-time config 52 /* Lane power-down */ 56 * initiates a logic reset. Self-clearing */ 63 /* Lane selection */ 69 /* Lane power-down */ 79 /* Bit position of value for lane 0 (or 2) */ 81 /* Bit position of value for lane 1 (or 3) */ [all …]
|
/openbmc/linux/drivers/gpu/drm/msm/dp/ |
H A D | dp_panel.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 77 * is_link_rate_valid() - validates the link rate 91 * dp_link_is_lane_count_valid() - validates the lane count 92 * @lane_count: lane count requested by the sink 94 * Returns true if the requested lane count is supported.
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
H A D | link_dp_training_fixed_vs_pe_retimer.c | 42 link->ctx->logger 52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local 54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust() 55 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust() 58 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1); in dp_fixed_vs_pe_read_lane_adjust() 60 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust() 63 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1); in dp_fixed_vs_pe_read_lane_adjust() 65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust() 66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust() 67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust() [all …]
|
H A D | link_dp_training_8b_10b.c | 36 link->ctx->logger 46 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_cr_training_aux_rd_interval() 72 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval() 100 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set; in decide_8b_10b_training_settings() 101 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set; in decide_8b_10b_training_settings() 102 lt_settings->link_settings.link_rate = link_setting->link_rate; in decide_8b_10b_training_settings() 103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings() 107 * path_mode->display_path) ? in decide_8b_10b_training_settings() 111 lt_settings->link_settings.link_spread = link->dp_ss_off ? in decide_8b_10b_training_settings() 113 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting); in decide_8b_10b_training_settings() [all …]
|
/openbmc/linux/include/linux/phy/ |
H A D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set 31 * lane 0, used for the transmissions on main link. 41 * to be used by particular lanes. One value per lane. 42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. 51 * Pre-emphasis levels, as specified by DisplayPort specification, to be 52 * used by particular lanes. One value per lane. 61 * Flag indicating, whether or not to enable spread-spectrum clocking. 78 * Flag indicating, whether or not reconfigure lane count to 88 * and pre-emphasis to requested values. Only lanes specified
|
/openbmc/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation 43 * IOSF-SB port. 46 * houses a common lane part which contains the PLL and other common 47 * logic. CH0 common lane also contains the IOSF-SB logic for the 57 * each spline is made up of one Physical Access Coding Sub-Layer 62 * Additionally the PHY also contains an AUX lane with AUX blocks 68 * Generally on VLV/CHV the common lane corresponds to the pipe and 101 * --------------------------------- 104 * |---------------|---------------| Display PHY 106 * |-------|-------|-------|-------| [all …]
|
H A D | intel_dp_link_training.c | 2 * Copyright © 2008-2015 Intel Corporation 30 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ 31 (_intel_dp)->attached_connector->base.name, \ 32 dp_to_dig_port(_intel_dp)->base.base.base.id, \ 33 dp_to_dig_port(_intel_dp)->base.base.name, \ 37 drm_dbg_kms(&dp_to_i915(_intel_dp)->drm, \ 42 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \ 43 drm_err(&dp_to_i915(_intel_dp)->drm, \ 52 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); in intel_dp_reset_lttpr_common_caps() 57 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - in intel_dp_reset_lttpr_count() [all …]
|
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/ |
H A D | high_speed_env_spec.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 21 /* Serdes revision 1.2 (for A38x-Z1) */ 23 /* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */ 27 #define SERDES_REGS_LANE_BASE_OFFSET(lane) (0x800 * (lane)) argument 32 /* Serdes lane types */ 217 int hws_board_topology_load(struct serdes_map **serdes_map, u8 *count); 222 int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count); 239 int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count); 246 int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count);
|
/openbmc/linux/drivers/edac/ |
H A D | thunderx_edac.c | 8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved. 56 while (descr->type && descr->mask && descr->descr) { in decode_register() 57 if (reg & descr->mask) { in decode_register() 59 descr->type == ERR_CORRECTED ? in decode_register() 61 descr->descr); in decode_register() 63 size -= ret; in decode_register() 71 return (data >> pos) & ((1 << width) - 1); in get_bits() 127 .descr = "Single-bit ECC error", 137 .descr = "Double-bit ECC error", 142 .descr = "Non-existent memory write", [all …]
|
/openbmc/u-boot/drivers/video/rockchip/ |
H A D | rk_edp.c | 1 // SPDX-License-Identifier: GPL-2.0+ 20 #include <dt-bindings/clock/rk3288-cru.h> 46 writel(SEL_24M, ®s->analog_ctl_2); in rk_edp_init_refclk() 47 writel(REF_CLK_24M, ®s->pll_reg_1); in rk_edp_init_refclk() 50 V2L_CUR_SEL_1MA, ®s->pll_reg_2); in rk_edp_init_refclk() 54 ®s->pll_reg_3); in rk_edp_init_refclk() 58 ®s->pll_reg_5); in rk_edp_init_refclk() 60 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg); in rk_edp_init_refclk() 64 ®s->tx_common); in rk_edp_init_refclk() 67 ®s->dp_aux); in rk_edp_init_refclk() [all …]
|
/openbmc/u-boot/doc/device-tree-bindings/video/bridge/ |
H A D | ps8622.txt | 1 ps8622-bridge bindings 4 - compatible: "parade,ps8622" or "parade,ps8625" 5 - reg: first i2c address of the bridge 6 - sleep-gpios: OF device-tree gpio specification for PD_ pin. 7 - reset-gpios: OF device-tree gpio specification for RST_ pin. 8 - parade,regs: List of 3-byte registers tuples to write: 12 - lane-count: number of DP lanes to use 13 - use-external-pwm: backlight will be controlled by an external PWM 14 - video interfaces: Device node can contain video interface port 17 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt [all …]
|
/openbmc/linux/drivers/thunderbolt/ |
H A D | debugfs.c | 1 // SPDX-License-Identifier: GPL-2.0 39 return single_open(file, __space ## _show, inode->i_private); \ 60 size_t *count) in validate_and_copy_from_user() argument 65 if (!*count) in validate_and_copy_from_user() 66 return ERR_PTR(-EINVAL); in validate_and_copy_from_user() 68 if (!access_ok(user_buf, *count)) in validate_and_copy_from_user() 69 return ERR_PTR(-EFAULT); in validate_and_copy_from_user() 73 return ERR_PTR(-ENOMEM); in validate_and_copy_from_user() 75 nbytes = min_t(size_t, *count, PAGE_SIZE); in validate_and_copy_from_user() 78 return ERR_PTR(-EFAULT); in validate_and_copy_from_user() [all …]
|
/openbmc/u-boot/drivers/ram/stm32mp1/ |
H A D | stm32mp1_ddr_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 13 u8 reserved008[0x10 - 0x8]; 20 u8 reserved028[0x30 - 0x28]; 24 u8 reserved03c[0x50 - 0x3C]; 31 u8 reserved068[0xc0 - 0x68]; 45 u8 reserved0f4[0x100 - 0xf4]; 55 u8 reserved124[0x138 - 0x124]; 58 u8 reserved140[0x180 - 0x140]; 72 u8 reserved1b4[0x1bc - 0x1b4]; [all …]
|
/openbmc/linux/drivers/net/ethernet/hisilicon/hns/ |
H A D | hns_dsaf_misc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright (c) 2014-2015 Hisilicon Limited. 35 if (dsaf_dev->sub_ctrl) in dsaf_write_sub() 36 dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val); in dsaf_write_sub() 38 dsaf_write_reg(dsaf_dev->sc_base, reg, val); in dsaf_write_sub() 46 if (dsaf_dev->sub_ctrl) { in dsaf_read_sub() 47 err = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg, &ret); in dsaf_read_sub() 49 dev_err(dsaf_dev->dev, "dsaf_read_syscon error %d!\n", in dsaf_read_sub() 52 ret = dsaf_read_reg(dsaf_dev->sc_base, reg); in dsaf_read_sub() 72 argv4.package.count = 3; in hns_dsaf_acpi_ledctrl_by_port() [all …]
|
/openbmc/linux/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix_dp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 83 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd() 85 if (!dp->force_hpd) in analogix_dp_detect_hpd() 86 return -ETIMEDOUT; in analogix_dp_detect_hpd() 93 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd() 98 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd() 99 return -EINVAL; in analogix_dp_detect_hpd() 102 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd() 112 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr() 114 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr() [all …]
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
H A D | link_dp_cts.c | 39 link->ctx->logger 84 struct dc_state *state = link->dc->current_state; in dp_retrain_link_dp_test() 85 uint8_t count; in dp_retrain_link_dp_test() local 90 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); in dp_retrain_link_dp_test() 92 for (i = 0; i < count; i++) { in dp_retrain_link_dp_test() 94 pipes[i]->link_config.dp_link_settings = *link_setting; in dp_retrain_link_dp_test() 96 link->dc, in dp_retrain_link_dp_test() 101 for (i = count-1; i >= 0; i--) in dp_retrain_link_dp_test() 123 link->verified_link_cap.lane_count = link_settings.lane_count; in dp_test_send_link_training() 124 link->verified_link_cap.link_rate = link_settings.link_rate; in dp_test_send_link_training() [all …]
|