Searched +full:jz4780 +full:- +full:uart (Results 1 – 9 of 9) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.0+3 #include <dt-bindings/clock/jz4780-cgu.h>6 #address-cells = <1>;7 #size-cells = <1>;8 compatible = "ingenic,jz4780";10 cpuintc: interrupt-controller {11 #address-cells = <0>;12 #interrupt-cells = <1>;13 interrupt-controller;14 compatible = "mti,cpu-interrupt-controller";[all …]
50 bool "Rockchip e-fuse support"53 Enable (read-only) access for the e-fuse block found in Rockchip55 or through child-nodes that are generated based on the e-fuse map74 Enable command-line access to the Chrome OS EC (Embedded76 a number of sub-commands for performing EC tasks such as112 keyboard (use the -l flag to enable the LCD), verified boot context,121 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface129 integrated 64-byte EEPROM, four programmable non-volatile I/O pins142 bool "Ingenic JZ4780 eFUSE support"145 This selects support for the eFUSE on Ingenic JZ4780 SoCs.[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * JZ4780 definitions90 void jz4780_clk_ungate_uart(const unsigned int uart);
1 // SPDX-License-Identifier: GPL-2.0+3 * JZ4780 PLL setup12 #include <mach/jz4780.h>362 ((((m) - 1) << 19) | (((n) - 1) << 13) | (((od) - 1) << 9))373 void __iomem *pll_reg = cpm_regs + CPM_CPAPCR + ((pll - 1) * 4); in pll_init_one()395 ((6 - 1) << CPM_CPCCR_H2DIV_BIT) | in cpu_mux_select()396 ((3 - 1) << CPM_CPCCR_H0DIV_BIT) | in cpu_mux_select()397 ((2 - 1) << CPM_CPCCR_L2DIV_BIT) | in cpu_mux_select()398 ((1 - 1) << CPM_CPCCR_CDIV_BIT); in cpu_mux_select()401 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT; in cpu_mux_select()[all …]
66 writeb(value, addr + (1 << shift) - 1); in serial_out_shift()83 return readb(addr + (1 << shift) - 1); in serial_in_shift()97 struct ns16550_platdata *plat = port->plat; in ns16550_writeb()100 offset *= 1 << plat->reg_shift; in ns16550_writeb()101 addr = (unsigned char *)plat->base + offset; in ns16550_writeb()105 * these options at run-time, so use the existing CONFIG options. in ns16550_writeb()107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); in ns16550_writeb()112 struct ns16550_platdata *plat = port->plat; in ns16550_readb()115 offset *= 1 << plat->reg_shift; in ns16550_readb()116 addr = (unsigned char *)plat->base + offset; in ns16550_readb()[all …]
1 // SPDX-License-Identifier: GPL-2.0+15 #include <mach/jz4780.h>116 /* UART 1 and 2 */ in ci20_mux_uart()230 if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */ in ci20_revision()240 gd->ram_size = sdram_size(0) + sdram_size(1); in dram_init()244 /* U-Boot common routines */
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1 2025-12-25 03:01:07.329-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler2 2025-12-25 03:01:07.402-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -[all...]
1 2025-12-24 03:01:02.878-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler2 2025-12-24 03:01:02.953-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -[all...]