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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsmsc,lan9115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dst,stm32-pinctrl.txt5 also provides ability to multiplex and configure the output of various on-chip
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
15 - ranges : defines mapping between pin controller node (parent) to
16 gpio-bank node (children).
17 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
22 - gpio-controller : Indicates this device is a GPIO controller
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
H A Dsemtech,sx1501q.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - semtech,sx1501q
17 - semtech,sx1502q
18 - semtech,sx1503q
19 - semtech,sx1504q
20 - semtech,sx1505q
21 - semtech,sx1506q
[all …]
H A Dcypress,cy8c95x0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrick Rudolph <patrick.rudolph@9elements.com>
14 Pin function configuration is performed on a per-pin basis.
19 - cypress,cy8c9520
20 - cypress,cy8c9540
21 - cypress,cy8c9560
26 gpio-controller: true
28 '#gpio-cells':
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/openbmc/linux/Documentation/driver-api/gpio/
H A Ddriver.rst26 between 0 and n-1, n being the number of GPIOs managed by the chip.
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
30 lines are handled by one bit per line in a 32-bit register, it makes sense to
44 So for example one platform could use global numbers 32-159 for GPIOs, with a
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
60 - methods to establish GPIO line direction
61 - methods used to access GPIO line values
62 - method to set electrical configuration for a given GPIO line
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dxive-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Each interrupt source has a 2-bit state machine called ESB
21 * needs to be re-triggered.
24 * manipulate the PQ bits. They must be used with an 8-bytes
41 * Load-after-store ordering
44 * load-after-store ordering. This is required to use StoreEOI.
46 #define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */
63 #define TM_NSR 0x0 /* + + - + */
64 #define TM_CPPR 0x1 /* - + - + */
65 #define TM_IPB 0x2 /* - + + + */
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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Qii Wang <qii.wang@mediatek.com>
22 - const: mediatek,mt2712-i2c
23 - const: mediatek,mt6577-i2c
24 - const: mediatek,mt6589-i2c
25 - const: mediatek,mt7622-i2c
[all …]
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
84 #define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))
121 return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE; in get_gpio_id()
137 r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': " in disconnect_all_pins()
138 "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }", in disconnect_all_pins()
151 r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':" in get_disconnected_pins()
152 " { 'path': %s, 'property': 'disconnected-pins'} }", path); in get_disconnected_pins()
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000-mps3.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 /dts-v1/;
14 compatible = "arm,corstone1000-mps3";
19 phy-mode = "mii";
21 reg-io-width = <2>;
22 smsc,irq-push-pull;
26 compatible = "nxp,usb-isp1763";
29 bus-width = <16>;
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb-bbrevd.dtsi26 compatible = "regulator-fixed";
27 regulator-name = "veth";
28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <3300000>;
30 regulator-boot-on;
40 phy-mode = "mii";
41 smsc,irq-active-high;
42 smsc,irq-push-pull;
43 vdd33a-supply = <&veth>;
44 vddvario-supply = <&veth>;
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7779-marzen.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) Marzen board
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
26 stdout-path = "serial0:115200n8";
34 fixedregulator3v3: regulator-3v3 {
35 compatible = "regulator-fixed";
36 regulator-name = "fixed-3.3V";
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H A Demev2-kzm9d.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
29 stdout-path = "serial1:115200n8";
33 compatible = "gpio-keys";
35 debounce-interval = <50>;
36 wakeup-source;
37 label = "DSW2-1";
[all …]
H A Dr8a73a4-ape6evm.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
36 vcc_mmc0: regulator-mmc0 {
37 compatible = "regulator-fixed";
38 regulator-name = "MMC0 Vcc";
39 regulator-min-microvolt = <2800000>;
40 regulator-max-microvolt = <2800000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/imu/
H A Dbosch,bmi160.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Cameron <jic23@kernel.org>
15 https://www.bosch-sensortec.com/bst/products/all_products/bmi160
27 interrupt-names:
29 - INT1
30 - INT2
35 drive-open-drain:
38 open drain. If not set, defaults to push-pull.
[all …]
/openbmc/linux/drivers/watchdog/
H A Daspeed_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
57 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
58 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
59 { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
90 * * Drive mode: push-pull vs open-drain
103 * and bit 30 represents push-pull or open-drain. With respect to write, magic
131 wdt->ctrl |= WDT_CTRL_ENABLE; in aspeed_wdt_enable()
133 writel(0, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
134 writel(count, wdt->base + WDT_RELOAD_VALUE); in aspeed_wdt_enable()
135 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_enable()
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8060-dragonboard.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/leds/common.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
7 #include "qcom-msm8660.dtsi"
11 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
18 stdout-path = "serial0:115200n8";
22 vph: regulator-fixed {
[all …]
/openbmc/qemu/include/hw/ppc/
H A Dxive_regs.h6 * architected to be big-endian. Some macros are provided to ease
10 * Copyright (c) 2016-2018, IBM Corporation.
13 * COPYING file in the top-level directory.
20 #include "qemu/host-utils.h"
52 * TIMA addresses are 12-bits (4k page).
55 * The registers, logically grouped in 4 rings (a quad-word each), are
74 #define TM_NSR 0x0 /* + + - + */
75 #define TM_CPPR 0x1 /* - + - + */
76 #define TM_IPB 0x2 /* - + + + */
77 #define TM_LSMFB 0x3 /* - + + + */
[all …]
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-ssbi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/pinctrl/pinconf-generic.h>
22 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
25 #include "../pinctrl-utils.h"
59 * struct pm8xxx_pin_data - dynamic configuration for a pin
64 * @open_drain: output buffer configured as open-drain (vs push-pull)
67 * @pull_up_strength: placeholder for selected pull up strength
68 * only used to configure bias when pull up is selected
69 * @output_strength: selector of output-strength
99 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0},
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-wm831x.c1 // SPDX-License-Identifier: GPL-2.0+
22 #include <linux/mfd/wm831x/irq.h>
32 struct wm831x *wm831x = wm831x_gpio->wm831x; in wm831x_gpio_direction_in()
35 if (wm831x->has_gpio_ena) in wm831x_gpio_direction_in()
46 struct wm831x *wm831x = wm831x_gpio->wm831x; in wm831x_gpio_get()
62 struct wm831x *wm831x = wm831x_gpio->wm831x; in wm831x_gpio_set()
72 struct wm831x *wm831x = wm831x_gpio->wm831x; in wm831x_gpio_direction_out()
76 if (wm831x->has_gpio_ena) in wm831x_gpio_direction_out()
94 struct wm831x *wm831x = wm831x_gpio->wm831x; in wm831x_gpio_to_irq()
96 return irq_create_mapping(wm831x->irq_domain, in wm831x_gpio_to_irq()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dmicrochip,cap11xx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Microchip CAP1xxx Family of RightTouchTM multiple-channel capacitive
14 - Rob Herring <robh@kernel.org>
19 - microchip,cap1106
20 - microchip,cap1126
21 - microchip,cap1188
22 - microchip,cap1203
23 - microchip,cap1206
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
27 stdout-path = "serial2:115200n8";
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
34 #clock-cells = <0>;
37 pmic_ap_clk: pmic-ap-clk {
39 compatible = "fixed-clock";
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx31-lite.dts1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
5 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "logicpd,imx31-lite", "fsl,imx31";
17 stdout-path = &uart1;
26 compatible = "gpio-leds";
43 nand-bus-width = <8>;
44 nand-ecc-mode = "hw";
[all …]
H A Dimx53-ard.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "fsl,imx53-ard", "fsl,imx53";
20 eim-cs1@f4000000 {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 compatible = "fsl,eim-bus", "simple-bus";
30 phy-mode = "mii";
31 interrupt-parent = <&gpio2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l36.txt5 - compatible : "cirrus,cs35l36"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
18 - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
24 - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value.
32 - cirrus,multi-amp-mode : Boolean to determine if there are more than
33 one amplifier in the system. If more than one it is best to Hi-Z the ASP
36 - cirrus,boost-ctl-select : Boost converter control source selection.
39 0x00 - Control Port Value
[all …]

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