hw/ppc/xive_regs.h

6  * architected to be big-endian. Some macros are provided to ease
10  * Copyright (c) 2016-2018, IBM Corporation.
13  * COPYING file in the top-level directory.
20 #include "qemu/host-utils.h"
52  * TIMA addresses are 12-bits (4k page).
55  * The registers, logically grouped in 4 rings (a quad-word each), are
74 #define TM_NSR                  0x0  /*  +   +   -   +  */
75 #define TM_CPPR                 0x1  /*  -   +   -   +  */
76 #define TM_IPB                  0x2  /*  -   +   +   +  */
77 #define TM_LSMFB                0x3  /*  -   +   +   +  */
78 #define TM_ACK_CNT              0x4  /*  -   +   -   -  */
79 #define TM_INC                  0x5  /*  -   +   -   +  */
81 #define TM_AGE                  0x6  /*  -   +   -   +  */
82 #define TM_T                    0x6  /*  -   +   -   +  */ /* Rename P10 */
83 #define TM_PIPR                 0x7  /*  -   +   -   +  */
84 #define TM_OGEN                 0xF  /*  -   +   -   -  */ /* P10 only */
111  *   - Byte load from QW0[NSR] - User level NSR (EBB)
112  *   - Byte store to QW0[NSR] - User level NSR (EBB)
113  *   - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
114  *   - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
116  *   - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
122 #define TM_SPC_ACK_OS_REG       0x810   /* Load16 ack OS irq to reg           */
123 #define TM_SPC_PUSH_USR_CTX     0x808   /* Store32 Push/Validate user context */
124 #define TM_SPC_PULL_USR_CTX     0x808   /* Load32 Pull/Invalidate user        */
126 #define TM_SPC_SET_OS_PENDING   0x812   /* Store8 Set OS irq pending bit      */
127 #define TM_SPC_PULL_OS_CTX_G2   0x810   /* Load32/Load64 Pull/Invalidate OS   */
129 #define TM_SPC_PULL_OS_CTX      0x818   /* Load32/Load64 Pull/Invalidate OS   */
131 #define TM_SPC_PULL_POOL_CTX_G2 0x820   /* Load32/Load64 Pull/Invalidate Pool */
133 #define TM_SPC_PULL_POOL_CTX    0x828   /* Load32/Load64 Pull/Invalidate Pool */
135 #define TM_SPC_ACK_HV_REG       0x830   /* Load16 ack HV irq to reg           */
136 #define TM_SPC_PULL_PHYS_CTX_G2 0x830   /* Load32 Pull phys ctx to reg        */
137 #define TM_SPC_PULL_PHYS_CTX    0x838   /* Load8  Pull phys ctx to reg        */
138 #define TM_SPC_PULL_USR_CTX_OL  0xc08   /* Store8 Pull/Inval usr ctx to odd   */
140 #define TM_SPC_ACK_OS_EL        0xc10   /* Store8 ack OS irq to even line     */
141 #define TM_SPC_PULL_OS_CTX_OL   0xc18   /* Pull/Invalidate OS context to      */
145 #define TM_SPC_ACK_HV_EL        0xc30   /* Store8 ack HV irq to even line     */
146 #define TM_SPC_PULL_PHYS_CTX_OL 0xc38   /* Pull phys ctx to odd cache line    */
169          * Use a single 64-bit definition to make it easier to perform
180 #define xive_eas_is_valid(eas)   (be64_to_cpu((eas)->w) & EAS_VALID)
181 #define xive_eas_is_masked(eas)  (be64_to_cpu((eas)->w) & EAS_MASKED)
220 #define END_W0_UNCOND_ESCALATE   PPC_BIT32(6) /* "u" bit - DD2.0 */
221 #define END_W0_SILENT_ESCALATE   PPC_BIT32(7) /* "s" bit - DD2.0 */
259 #define xive_end_is_valid(end)    (be32_to_cpu((end)->w0) & END_W0_VALID)
260 #define xive_end_is_enqueue(end)  (be32_to_cpu((end)->w0) & END_W0_ENQUEUE)
261 #define xive_end_is_notify(end)   (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY)
262 #define xive_end_is_backlog(end)  (be32_to_cpu((end)->w0) & END_W0_BACKLOG)
263 #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
265     (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE)
267     (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE)
269     (be32_to_cpu((end)->w0) & END_W0_FIRMWARE)
273     return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 |  in xive_end_qaddr()
274         be32_to_cpu(end->w3);  in xive_end_qaddr()
306 #define xive_nvt_is_valid(nvt)    (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
322     return cam_line & ((1 << XIVE_NVT_SHIFT) - 1);  in xive_nvt_idx()