| /openbmc/qemu/hw/i386/ |
| H A D | intel_iommu_internal.h | 60 #define DMAR_IQH_REG 0x80 /* Invalidation queue head */
62 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail */
64 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr */
66 #define DMAR_ICS_REG 0x9c /* Invalidation complete status */
69 #define DMAR_IECTL_REG 0xa0 /* Invalidation event control */
70 #define DMAR_IEDATA_REG 0xa4 /* Invalidation event data */
71 #define DMAR_IEADDR_REG 0xa8 /* Invalidation event address */
72 #define DMAR_IEUADDR_REG 0xac /* Invalidation event address */
123 #define VTD_TLB_GLOBAL_FLUSH (1ULL << 60) /* Global invalidation */
323 /* Interrupt Entry Cache Invalidation Descriptor: VT-d 6.5.2.7. */
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| H A D | intel_iommu.c | 611 /* Handle Invalidation Queue Errors of queued invalidation interface error
622 /* Set the IWC field and try to generate an invalidation completion interrupt */
1988 * capture it via the context entry invalidation, then the in vtd_do_iommu_translate()
2062 /* Notify global invalidation */ in vtd_interrupt_remap_table_setup()
2089 * From VT-d spec 6.5.2.1, a global context entry invalidation in vtd_context_global_invalidate()
2090 * should be followed by a IOTLB global invalidation, so we should in vtd_context_global_invalidate()
2098 /* Do a context-cache device-selective invalidation.
2160 /* Context-cache invalidation
2161 * Returns the Context Actual Invalidation Granularity.
2281 * Returns the IOTLB Actual Invalidation Granularity.
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | tlbflush.h | 95 * the level at which the invalidation must take place. If the level is
96 * wrong, no invalidation may take place. In the case where the level
98 * perform a non-hinted invalidation.
100 * For Stage-2 invalidation, use the level values provided to that effect
169 * TLB Invalidation
172 * This header file implements the low-level TLB invalidation routines
175 * Every invalidation operation uses the following template:
179 * DSB ISH // Ensure the TLB invalidation has completed
184 * The following functions form part of the "core" TLB invalidation API,
214 * Next, we have some undocumented invalidation routines that you probably
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| H A D | kvm_pgtable.h | 218 * TLB invalidation.
370 * to freeing and therefore no TLB invalidation is performed.
406 * TLB invalidation is performed for each page-table entry cleared during the
465 * to freeing and therefore no TLB invalidation is performed.
476 * freeing and therefore no TLB invalidation is performed.
493 * invalidation or CMOs are performed.
568 * TLB invalidation is performed for each page-table entry cleared during the
580 * without TLB invalidation.
644 * TLB invalidation is performed after updating the entry. Software bits cannot
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| /openbmc/qemu/include/hw/i386/ |
| H A D | x86-iommu.h | 46 * triggered when IR invalidation happens.
48 * @global: whether this is a global IEC invalidation
50 * @mask: invalidation mask
150 * @global: whether this is a global invalidation. If true, @index
153 * @mask: index mask for the invalidation
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| /openbmc/u-boot/doc/ |
| H A D | README.arm-caches | 31 it. This may be needed in addition to the invalidation before the DMA
40 - If the buffer is not cache-line aligned invalidation will be restricted
42 may be left out while doing invalidation.
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| /openbmc/linux/drivers/iommu/intel/ |
| H A D | dmar.c | 1215 return "Context-cache Invalidation"; in qi_type_string()
1217 return "IOTLB Invalidation"; in qi_type_string()
1219 return "Device-TLB Invalidation"; in qi_type_string()
1221 return "Interrupt Entry Cache Invalidation"; in qi_type_string()
1223 return "Invalidation Wait"; in qi_type_string()
1225 return "PASID-based IOTLB Invalidation"; in qi_type_string()
1227 return "PASID-cache Invalidation"; in qi_type_string()
1229 return "PASID-based Device-TLB Invalidation"; in qi_type_string()
1244 pr_err("VT-d detected Invalidation Queue Error: Reason %llx", in qi_dump_fault()
1247 pr_err("VT-d detected Invalidation Time-out Error: SID %llx", in qi_dump_fault()
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| H A D | iommu.h | 80 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
81 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
82 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
83 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
84 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
85 #define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */
338 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
339 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
340 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
430 /* PASID cache invalidation granu */
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| /openbmc/linux/drivers/infiniband/ulp/rtrs/ |
| H A D | README | 54 The procedure is the default behaviour of the driver. This invalidation and
165 the user header, flags (specifying if memory invalidation is necessary) and the
169 attaches an invalidation message if requested and finally an "empty" rdma
176 or in case client requested invalidation:
184 the user header, flags (specifying if memory invalidation is necessary) and the
190 attaches an invalidation message if requested and finally an "empty" rdma
201 or in case client requested invalidation:
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| /openbmc/qemu/linux-headers/linux/ |
| H A D | iommufd.h | 627 * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
629 * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
637 * stage-1 cache invalidation
638 * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
647 * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
655 * The Intel VT-d specific invalidation data for user-managed stage-1 cache
656 * invalidation in nested translation. Userspace uses this structure to
674 * @hwpt_id: ID of a nested HWPT for cache invalidation
675 * @data_uptr: User pointer to an array of driver-specific cache invalidation
678 * type of all the entries in the invalidation request array. It
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | pnv-ocxl.h | 19 /* Radix Invalidation Control
28 /* Invalidation Criteria
35 /* Invalidation Flag */
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| /openbmc/linux/arch/arm64/kvm/hyp/vhe/ |
| H A D | tlb.c | 101 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
104 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
133 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
136 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa_nsh()
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| /openbmc/linux/arch/arm64/kvm/hyp/nvhe/ |
| H A D | tlb.c | 26 * being either ish or nsh, depending on the invalidation in __tlb_switch_to_guest()
98 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
101 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
150 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
153 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa_nsh()
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| /openbmc/linux/arch/arm/mach-versatile/ |
| H A D | dcscb_setup.S | 20 * A15/A7 may not require explicit L2 invalidation on reset, dependent
23 * or invalidation is not required.
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| /openbmc/linux/Documentation/filesystems/caching/ |
| H A D | netfs-api.rst | 36 (8) Data file invalidation
39 (11) Page release and invalidation
285 The read operation will fail with ESTALE if invalidation occurred whilst the
302 Data File Invalidation
319 This increases the invalidation counter in the cookie to cause outstanding
324 Invalidation runs asynchronously in a worker thread so that it doesn't block
427 Page Release and Invalidation
442 Page release and page invalidation should also wait for any mark left on the
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_tlb.c | 17 * HW architecture suggest typical invalidation time at 40us,
25 * On Xe_HP the TLB invalidation registers are located at the same MMIO offsets
99 "%s TLB invalidation did not complete in %ums!\n", in mmio_invalidate_full()
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| /openbmc/linux/include/linux/ |
| H A D | memregion.h | 41 * contents while performing the invalidation. It is only exported for
59 WARN_ON_ONCE("CPU cache invalidation required"); in cpu_cache_invalidate_memregion()
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| H A D | io-pgtable.h | 32 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
33 * single page. IOMMUs that cannot batch TLB invalidation
36 * and defer the invalidation until iommu_iotlb_sync() instead.
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| /openbmc/linux/drivers/cxl/ |
| H A D | Kconfig | 133 to invalidate caches when those events occur. If that invalidation
135 invalidation failure are due to the CPU not providing a cache
136 invalidation mechanism. For example usage of wbinvd is restricted to
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| /openbmc/u-boot/arch/arm/cpu/armv7/ |
| H A D | cache_v7.c | 89 /* Full system DSB - make sure that the invalidation is complete */ in v7_inval_tlb()
103 * Performs a clean & invalidation of the entire data cache
195 /* Full system DSB - make sure that the invalidation is complete */ in invalidate_icache_all()
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| /openbmc/linux/drivers/misc/sgi-gru/ |
| H A D | grutlbpurge.c | 32 /* ---------------------------------- TLB Invalidation functions --------
86 * General purpose TLB invalidation function. This function scans every GRU in
115 * To help improve the efficiency of TLB invalidation, the GMS data
120 * provide the callbacks for TLB invalidation. The GMS contains:
137 * zero to force a full TLB invalidation. This is fast but will
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gmc_v11_0.c | 212 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v11_0_flush_vm_hub()
213 * release after invalidation to avoid entering power gated state in gmc_v11_0_flush_vm_hub()
248 * add semaphore release after invalidation, in gmc_v11_0_flush_vm_hub()
254 /* Issue additional private vm invalidation to MMHUB */ in gmc_v11_0_flush_vm_hub()
261 /* Issue private invalidation */ in gmc_v11_0_flush_vm_hub()
263 /* Read back to ensure invalidation is done*/ in gmc_v11_0_flush_vm_hub()
295 * Directly use kiq to do the vm invalidation instead in gmc_v11_0_flush_gpu_tlb()
322 * @inst: is used to select which instance of KIQ to use for the invalidation
391 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v11_0_emit_flush_gpu_tlb()
392 * release after invalidation to avoid entering power gated state in gmc_v11_0_emit_flush_gpu_tlb()
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | l2cr_6xx.S | 60 - L2I set to perform a global invalidation
111 /* Before we perform the global invalidation, we must disable dynamic
207 /* Perform a global invalidation */
223 /* Wait for the invalidation to complete */
342 /* Perform a global invalidation */
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | l2_cache.json | 12 …he L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line …
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | l2_cache.json | 12 …he L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line …
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
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