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Searched +full:int +full:- +full:clock +full:- +full:stable +full:- +full:broken (Results 1 – 25 of 39) sorted by relevance

12

/openbmc/linux/kernel/sched/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
18 * clock with bounded drift between CPUs. The value of cpu_clock(i)
29 * cpu_clock(i) -- can be used from any context, including NMI.
30 * local_clock() -- is cpu_clock() on the current CPU.
41 * Otherwise it tries to create a semi stable clock from a mixture of other
44 * - GTOD (clock monotonic)
45 * - sched_clock()
46 * - explicit idle events
58 * Scheduler clock - returns current time in nanosec units.
60 * Architectures and sub-architectures can override this.
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 1991-2002 Linus Torvalds
27 #include <linux/sched/clock.h>
70 # include <linux/entry-common.h>
96 #include "../../io_uring/io-wq.h"
130 const_debug unsigned int sysctl_sched_features =
142 __read_mostly int sysctl_resched_latency_warn_ms = 100;
143 __read_mostly int sysctl_resched_latency_warn_once = 1;
150 const_debug unsigned int sysctl_sched_nr_migrate = SCHED_NR_MIGRATE_BREAK;
152 __read_mostly int scheduler_running;
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/openbmc/linux/include/linux/
H A Dfsl_devices.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 PHY CLK to become stable - 10ms*/
30 * Each sub-arch has its own master list of unique devices and
31 * enumerates them by enum fsl_devices in a sub-arch specific header
33 * The platform data structure is broken into two parts. The
40 * - platform data structures: <driver>_platform_data
41 * - platform data device flags: FSL_<driver>_DEV_<FLAG>
42 * - platform data board flags: FSL_<driver>_BRD_<FLAG>
47 FSL_USB_VER_NONE = -1,
79 unsigned int port_enables;
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/openbmc/linux/drivers/gpu/drm/pl111/
H A Dpl111_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
7 * Copyright (c) 2006-2008 Intel Corporation
14 #include <linux/dma-buf.h>
15 #include <linux/media-bus-format.h>
27 irqreturn_t pl111_irq(int irq, void *data) in pl111_irq()
33 irq_stat = readl(priv->regs + CLCD_PL111_MIS); in pl111_irq()
39 drm_crtc_handle_vblank(&priv->pipe.crtc); in pl111_irq()
45 writel(irq_stat, priv->regs + CLCD_PL111_ICR); in pl111_irq()
54 struct drm_device *drm = pipe->crtc.dev; in pl111_mode_valid()
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/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/mmc/slot-gpio.h>
24 #include "sdhci-pltfm.h"
36 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
41 unsigned int divider_for_baseclk;
57 mc1r = readb(host->ioaddr + SDMMC_MC1R); in sdhci_at91_set_force_card_detect()
59 writeb(mc1r, host->ioaddr + SDMMC_MC1R); in sdhci_at91_set_force_card_detect()
62 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) in sdhci_at91_set_clock() argument
66 host->mmc->actual_clock = 0; in sdhci_at91_set_clock()
69 * There is no requirement to disable the internal clock before in sdhci_at91_set_clock()
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H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
79 /* Default settings for ZynqMP Clock Phases */
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
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H A Dsdhci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
103 * VDD2 - UHS2 or PCIe/NVMe
174 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
196 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
243 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
252 /* 4C-4F reserved for more max current */
259 /* 55-57 reserved */
264 /* 60-FB reserved */
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H A Dsdhci-pci-o2micro.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "sdhci-pci.h"
101 mmc_hostname(host->mmc)); in sdhci_o2_wait_card_detect_stable()
136 pr_err("%s: Internal clock never stabilised.\n", in sdhci_o2_enable_internal_clock()
137 mmc_hostname(host->mmc)); in sdhci_o2_enable_internal_clock()
155 static int sdhci_o2_get_cd(struct mmc_host *mmc) in sdhci_o2_get_cd()
171 pci_read_config_dword(chip->pdev, in o2_pci_set_baseclk()
177 pci_write_config_dword(chip->pdev, in o2_pci_set_baseclk()
192 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) in sdhci_o2_wait_dll_detect_lock()
212 int i; in __sdhci_o2_execute_tuning()
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H A Dsdhci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
9 * - JMicron (hardware and technical support)
19 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
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/openbmc/linux/Documentation/process/
H A Dmaintainer-tip.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------------
11 aggregation tree for several sub-maintainer trees. The tip tree gitweb URL
16 - **x86 architecture**
22 x86-specific KVM and XEN patches.
30 mail alias which distributes mails to the x86 top-level maintainer
32 ``linux-kernel@vger.kernel.org``, otherwise your mail ends up only in
35 - **Scheduler**
37 Scheduler development takes place in the -tip tree, in the
38 sched/core branch - with occasional sub-topic trees for
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/openbmc/u-boot/arch/arm/mach-tegra/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
6 /* Tegra SoC common clock control functions */
13 #include <asm/arch/clock.h>
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/timer.h>
21 * This is our record of the current clock rate of each clock. We don't
50 /* number of clock outputs of a PLL */
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/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Datomisp_gmin_platform.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-subdev.h>
29 /* Valid clock number range from 0 to 5 */
32 /* X-Powers AXP288 register set */
80 unsigned int csi_lanes;
90 int v1p8_gpio;
91 int v2p8_gpio;
96 int eldo1_sel_reg, eldo1_1p6v, eldo1_ctrl_shift;
97 int eldo2_sel_reg, eldo2_1p8v, eldo2_ctrl_shift;
126 static int gmin_v1p8_enable_count;
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/openbmc/linux/drivers/media/usb/uvc/
H A Duvc_video.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * uvc_video.c -- USB Video Class driver - Video handling
5 * Copyright (C) 2005-2010
9 #include <linux/dma-mapping.h>
23 #include <media/v4l2-common.h>
27 /* ------------------------------------------------------------------------
31 static int __uvc_query_ctrl(struct uvc_device *dev, u8 query, u8 unit, in __uvc_query_ctrl()
33 int timeout) in __uvc_query_ctrl()
36 unsigned int pipe; in __uvc_query_ctrl()
38 pipe = (query & 0x80) ? usb_rcvctrlpipe(dev->udev, 0) in __uvc_query_ctrl()
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/openbmc/linux/arch/x86/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "64-bit kernel" if "$(ARCH)" = "x86"
7 Say yes to build a 64-bit kernel - formerly known as x86_64
8 Say no to build a 32-bit kernel - formerly known as i386
13 # Options that are inherently 32-bit kernel only:
27 # Options that are inherently 64-bit kernel only:
54 # ported to 32-bit as well. )
141 # Word-size accesses may read uninitialized data past the trailing \0
315 default "elf32-i386" if X86_32
316 default "elf64-x86-64" if X86_64
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/openbmc/linux/drivers/video/fbdev/
H A Dpvr2fb.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (c) 2001 - 2008 Paul Mundt <lethal@linux-sh.org>
13 * here are some hacked-up formulas:
19 * values, I could just add mode- specific offsets to get the correct mode
22 * left_margin = diwstart_h - borderstart_h;
23 * right_margin = borderstop_h - (diwstart_h + xres);
24 * upper_margin = diwstart_v - borderstart_v;
25 * lower_margin = borderstop_v - (diwstart_h + yres);
27 * hsync_len = borderstart_h + (hsync_total - borderstop_h);
28 * vsync_len = borderstart_v + (vsync_total - borderstop_v);
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/openbmc/qemu/qapi/
H A Dblock-core.json1 # -*- Mode: Python -*-
20 # @vm-state-size: size of the VM state
22 # @date-sec: UTC date of the snapshot in seconds
24 # @date-nsec: fractional part in nano seconds to be used with date-sec
26 # @vm-clock-sec: VM clock relative to boot in seconds
28 # @vm-clock-nsec: fractional part in nano seconds to be used with
29 # vm-clock-sec
32 # record/replay is enabled. Used for "time-traveling" to match
34 # counter may be obtained through @query-replay command (since
40 'data': { 'id': 'str', 'name': 'str', 'vm-state-size': 'int',
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/openbmc/linux/drivers/crypto/
H A Dhifn_795x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
30 "PLL reference clock (pci[freq] or ext[freq], default ext)");
199 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
208 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
217 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
227 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
272 #define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */
273 #define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */
274 #define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */
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/openbmc/linux/arch/x86/kvm/
H A Dx86.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
16 * Ben-Ami Yassour <benami@il.ibm.com>
48 #include <linux/user-return-notifier.h>
62 #include <linux/entry-kvm.h>
103 ((struct kvm_vcpu *)(ctxt)->vcp
2262 struct pvclock_clock clock; /* extract of a clocksource struct */ global() member
2815 vgettsc(struct pvclock_clock * clock,u64 * tsc_timestamp,int * mode) vgettsc() argument
12201 bool stable, backwards_tsc = false; kvm_arch_hardware_enable() local
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/openbmc/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
33 static int prepare_refcnt;
34 static int enable_refcnt;
57 int index;
80 unsigned int enable_count;
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/openbmc/linux/drivers/input/serio/
H A Di8042.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 1999-2004 Vojtech Pavlik
59 static int i8042_set_reset(const char *val, const struct kernel_param *kp) in i8042_set_reset()
61 enum i8042_controller_reset_mode *arg = kp->arg; in i8042_set_reset()
62 int error; in i8042_set_reset()
88 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
130 …enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-c…
159 int irq;
181 static irqreturn_t i8042_interrupt(int irq, void *dev_id);
197 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, in i8042_install_filter()
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp.c107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
119 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
127 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
132 intel_dp->sink_rates[0] = 162000; in intel_dp_set_default_sink_rates()
133 intel_dp->num_sink_rates = 1; in intel_dp_set_default_sink_rates()
139 static const int dp_rates[] = { in intel_dp_set_dpcd_sink_rates()
142 int i, max_rate; in intel_dp_set_dpcd_sink_rates()
143 int max_lttpr_rate; in intel_dp_set_dpcd_sink_rates()
145 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { in intel_dp_set_dpcd_sink_rates()
147 static const int quirk_rates[] = { 162000, 270000, 324000 }; in intel_dp_set_dpcd_sink_rates()
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/openbmc/linux/drivers/net/phy/
H A Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
118 * each nsec contains 4 clock cycles.
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
320 int hwts_tx_type;
322 int layer;
323 int version;
339 int led_mode;
403 static int kszphy_extended_write(struct phy_device *phydev, in kszphy_extended_write()
410 static int kszphy_extended_read(struct phy_device *phydev, in kszphy_extended_read()
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/openbmc/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
19 Format: <int>
26 If set to vendor, prefer vendor-specific driver
35 64 bit X_* addresses. Some firmware have broken 64
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/openbmc/qemu/hw/arm/
H A Dvirt.c2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
25 * and also because it reduces our exposure to being broken when
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
56 #include "qemu/error-report.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
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