instruction (full) in projects: openbmc

Searched full:instruction (Results 1 – 25 of 3036) sorted by relevance

/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	frontend.json	5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct… 11 "BriefDescription": "Branch Instruction Finished", 23 "BriefDescription": "Branch Instruction completed", 71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch", 72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch" 89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different … 90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different … 95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No… 96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No… 101 …: "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Gr… [all …]
H A D	other.json	305 "BriefDescription": "Completion stall due to VSU scalar instruction", 311 "BriefDescription": "Completion stall due to VSU scalar long latency instruction", 323 "BriefDescription": "Completion stall due to VSU vector instruction", 329 "BriefDescription": "Completion stall due to VSU vector long instruction", 335 "BriefDescription": "Completion stall due to VSU instruction", 359 "BriefDescription": "IFU Finished a (non-branch) instruction", 713 "BriefDescription": "Dispatch/CLB Hold: Sync type instruction", 887 "BriefDescription": "Convert instruction executed", 893 "BriefDescription": "Estimate instruction executed", 899 "BriefDescription": "Round to single precision instruction executed", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	metrics.json	10 "BriefDescription": "Average cycles per completed instruction", 16 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled for any re… 22 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled because th… 28 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled because Fe… 34 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled because th… 40 …cription": "Average cycles per completed instruction when dispatch was stalled waiting to resolve … 46 …cription": "Average cycles per completed instruction when dispatch was stalled waiting to resolve … 52 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to an … 58 …iefDescription": "Average cycles per completed instruction when dispatch was stalled while the ins… 64 …iefDescription": "Average cycles per completed instruction when dispatch was stalled while the ins… [all …]
H A D	pipeline.json	5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or… 10 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch fo… 20 "BriefDescription": "MMA instruction issued." 35 "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss." 40 "BriefDescription": "The instruction was flushed after becoming next-to-complete (NTC)." 50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 55 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a… 75 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be… 80 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be… [all …]
H A D	marked.json	5 …instruction issued. Note that stores always get issued twice, the address gets issued to the LSU a… 15 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel… 35 "BriefDescription": "The thread has dispatched a randomly sampled marked instruction." 40 "BriefDescription": "Marked Branch Taken instruction completed." 45 "BriefDescription": "Marked instruction suffered an instruction cache miss." 55 "BriefDescription": "Marked instruction RC dispatched in L2." 60 …"BriefDescription": "Cycles in which the marked instruction is the oldest in the pipeline (next-to… 65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 70 …"BriefDescription": "The marked instruction was a decimal floating point operation issued to the V… 75 …"BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measure… [all …]
H A D	floating_point.json	5 …ompleted. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1\|2\|4\|8… 10 …"BriefDescription": "One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs,… 15 …"BriefDescription": "Four floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs… 20 …"BriefDescription": "Two floating point instruction completed (FMA class of instructions: fmadd, f… 25 "BriefDescription": "Scalar floating point instruction completed." 30 "BriefDescription": "Single Precision floating point instruction completed." 35 "BriefDescription": "Math floating point instruction completed." 45 "BriefDescription": "Four Double Precision vector instruction completed." 50 "BriefDescription": "Non FMA instruction completed." 55 "BriefDescription": "Vector floating point instruction completed." [all …]
/openbmc/qemu/disas/
H A D	nanomips.c	26 * [1] "MIPS® Architecture Base: nanoMIPS32(tm) Instruction Set Technical 338 * Used in handling following instruction: 502 static uint64 extract_code_18_to_0(uint64 instruction) in extract_code_18_to_0() argument 505 value \|= extract_bits(instruction, 0, 19); in extract_code_18_to_0() 510 static uint64 extract_shift3_2_1_0(uint64 instruction) in extract_shift3_2_1_0() argument 513 value \|= extract_bits(instruction, 0, 3); in extract_shift3_2_1_0() 518 static uint64 extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction) in extract_u_11_10_9_8_7_6_5_4_3__s3() argument 521 value \|= extract_bits(instruction, 3, 9) << 3; in extract_u_11_10_9_8_7_6_5_4_3__s3() 526 static uint64 extract_count_3_2_1_0(uint64 instruction) in extract_count_3_2_1_0() argument 529 value \|= extract_bits(instruction, 0, 4); in extract_count_3_2_1_0() [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 39 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 42 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/openbmc/linux/Documentation/virt/kvm/s390/
H A D	s390-pv.rst	26 the behavior of the SIE instruction. A new format 4 state description 48 of an instruction emulation by KVM, e.g. we can never inject a 63 Instruction emulation 65 With the format 4 state description for PVMs, the SIE instruction already 67 to interpret every instruction, but needs to hand some tasks to KVM; 71 Instruction Data Area (SIDA), the Interception Parameters (IP) and the 73 the instruction data, such as I/O data structures, are filtered. 74 Instruction data is copied to and from the SIDA when needed. Guest 78 Only GR values needed to emulate an instruction will be copied into this 82 the bytes of the instruction text, but with pre-set register values [all …]
/openbmc/qemu/tcg/loongarch64/
H A D	tcg-insn-defs.c.inc	3 * LoongArch instruction formats, opcodes, and encoders for TCG use. 1318 /* Emits the `movgr2scr td, j` instruction. / 1325 / Emits the `movscr2gr d, tj` instruction. / 1332 / Emits the `clz.w d, j` instruction. / 1339 / Emits the `ctz.w d, j` instruction. / 1346 / Emits the `clz.d d, j` instruction. / 1353 / Emits the `ctz.d d, j` instruction. / 1360 / Emits the `revb.2h d, j` instruction. / 1367 / Emits the `revb.2w d, j` instruction. / 1374 / Emits the `revb.d d, j` instruction. */ [all …]
/openbmc/linux/arch/sh/kernel/
H A D	traps_32.c	96 * handle an instruction that does an unaligned memory access by emulating the 98 * - note that PC _may not_ point to the faulting instruction 99 * (if that instruction is in a branch delay slot) 102 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs regs, in handle_unaligned_ins() argument 110 index = (instruction>>8)&15; / 0x0F00 / in handle_unaligned_ins() 113 index = (instruction>>4)&15; / 0x00F0 */ in handle_unaligned_ins() 116 count = 1<<(instruction&3); in handle_unaligned_ins() 126 switch (instruction>>12) { in handle_unaligned_ins() 128 if (instruction & 8) { in handle_unaligned_ins() 160 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins() [all …]
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	translation.json	20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed" 35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request" 45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin… 50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)" 55 …: "Cycles during which the marked instruction is next to complete (completion is held up because t… 65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi… 75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request" 80 …": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on … 100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request" 115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t… [all …]
H A D	frontend.json	5 …B with Modified (M) data from another core's L3 on the same chip due to a instruction side request" 15 …aded into the TLB from a location other than the local core's L3 due to a instruction side request" 20 …"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in t… 25 …instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ… 40 … or the original scope was System and it should have been smaller. Counts for an instruction fetch" 45 "BriefDescription": "Marked Instruction RC dispatched in L2" 60 … Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch" 70 …Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. … 75 …s finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an ad… 80 …e. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to c… [all …]
H A D	marked.json	5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n… 15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at… 35 …cription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conf… 65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 75 "BriefDescription": "Vector FP instruction completed" 80 …Description": "The processor's Instruction cache was reloaded from local core's L2 without conflic… 85 …ription": "The processor's Instruction cache was reloaded from a location other than the local cor… 90 …ch the NTC instruction is not allowed to complete because it was interrupted by ANY exception, whi… 115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB" 120 …: "The processor's Instruction cache was reloaded from another chip's memory on the same Node or G… [all …]
H A D	cache.json	10 …"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of… 15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi… 20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p… 35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and… 40 … processor's Instruction cache was reloaded either shared or modified data from another core's L2/… 45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its … 50 …n": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Gro… 55 … Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node… 90 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor… 100 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Nod… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	13 …Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is… 18 …"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both ca… 21 …ion": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streamin… 26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 34 …"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includ… 37 …"PublicDescription": "This event counts the number of instruction cache, streaming buffer and vict… 46 …n": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (I… 55 …ion": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (I… 64 …n": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (I… 73 …tion": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (I… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	frontend.json	13 …Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is… 18 …"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both ca… 21 …ion": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streamin… 26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 34 …"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includ… 37 …"PublicDescription": "This event counts the number of instruction cache, streaming buffer and vict… 46 …n": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (I… 55 …ion": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (I… 64 …n": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (I… 73 …tion": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (I… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	frontend.json	13 …Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is… 18 …"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both ca… 21 …ion": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streamin… 26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 34 …"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includ… 37 …"PublicDescription": "This event counts the number of instruction cache, streaming buffer and vict… 46 …n": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (I… 55 …ion": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (I… 64 …n": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (I… 73 …tion": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (I… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A D	extended.json	42 … Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is … 49 …request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress … 77 …"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mo… 84 …"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-executio… 202 …"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cach… 203 …"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory… 209 …"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cach… 210 …"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory… 216 …"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cach… 217 …"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory… [all …]
/openbmc/u-boot/doc/imx/mkimage/
H A D	mxsimage.txt	23 Each configuration file uses very simple instruction semantics and a few 27 - Each line of the configuration file contains exactly one instruction. 31 - Each "section" is started by the "SECTION" instruction. 32 - The "SECTION" instruction has the following semantics: 43 - A "SECTION" must be immediatelly followed by a "TAG" instruction. 44 - The "TAG" instruction has the following semantics: 49 - After a "TAG" instruction, any of the following instructions may follow 53 - This instruction does nothing 62 - i.MX28-specific instruction! 67 - i.MX28-specific instruction! [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	frontend.json	6 …is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a … 11 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al… 14 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the … 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Cr… 65 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis… 70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 81 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 87 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	frontend.json	6 …is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a … 11 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al… 14 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the … 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Cr… 65 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis… 70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 81 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 87 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	frontend.json	6 …is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a … 11 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al… 14 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the … 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Cr… 65 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis… 70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 81 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 87 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A D	common-and-microarch.json	3 …"PublicDescription": "Instruction architecturally executed, Condition code check pass, software in… 6 …"BriefDescription": "Instruction architecturally executed, Condition code check pass, software inc… 9 "PublicDescription": "Level 1 instruction cache refill", 12 "BriefDescription": "Level 1 instruction cache refill" 15 "PublicDescription": "Attributable Level 1 instruction TLB refill", 18 "BriefDescription": "Attributable Level 1 instruction TLB refill" 39 … "PublicDescription": "Instruction architecturally executed, condition code check pass, load", 42 "BriefDescription": "Instruction architecturally executed, condition code check pass, load" 45 … "PublicDescription": "Instruction architecturally executed, condition code check pass, store", 48 "BriefDescription": "Instruction architecturally executed, condition code check pass, store" [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	frontend.json	6 …is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a … 11 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al… 14 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the … 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Cr… 65 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis… 70 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 76 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 81 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 87 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", [all …]

12 3 4 5 6 7 8 9 10 >>...122

Project(s)

Full Search
Definition
Symbol
File Path
History
Type