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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qm-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg";
11 #clock-cells = <1>;
12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 clock-output-names = "uart4_lpcg_baud_clk",
17 power-domains = <&pd IMX_SC_R_UART_4>;
20 can1_lpcg: clock-controller@5ace0000 {
[all …]
H A Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dma_ipg_clk: clock-dma-ipg {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
H A Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dimx8-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 lsio_mem_clk: clock-lsio-mem {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
[all …]
H A Dimx8-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 conn_axi_clk: clock-conn-axi {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
H A Dimx8dxl-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
18 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
20 interrupt-parent = <&gic>;
[all …]
H A Dimx8dxl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
H A Dimx8qxp-ai_ml.dts1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
9 #include "imx8qxp.dtsi"
13 compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
22 stdout-path = &lpuart2;
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_leds>;
35 user-led1 {
38 linux,default-trigger = "heartbeat";
[all …]
H A Dimx8qxp-mek.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include "imx8qxp.dtsi"
9 #include <dt-bindings/usb/pd.h>
13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
16 stdout-path = &lpuart0;
24 reg_usdhc2_vmmc: usdhc2-vmmc {
25 compatible = "regulator-fixed";
26 regulator-name = "SD1_SPWR";
27 regulator-min-microvolt = <3000000>;
[all …]
H A Dimx8qm.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dnxp,imx8qxp-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP IMX8QXP ADC
10 - Cai Huoqing <caihuoqing@baidu.com>
13 Supports the ADC found on the IMX8QXP SoC.
17 const: nxp,imx8qxp-adc
28 clock-names:
30 - const: per
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,scu-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol
10 - Abel Vesa <abel.vesa@nxp.com>
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
15 (Documentation/devicetree/bindings/clock/clock-bindings.txt)
18 include/dt-bindings/clock/imx8qxp-clock.h
23 - enum:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
[all …]
/openbmc/linux/drivers/clk/imx/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
[all …]
H A Dclk-imx8qxp-lpcg.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
16 #include "clk-scu.h"
17 #include "clk-imx8qxp-lpcg.h"
19 #include <dt-bindings/clock/imx8-clock.h>
22 * struct imx8qxp_lpcg_data - Description of one LPCG clock
44 * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
166 unsigned int idx = clkspec->args[0] / 4; in imx_lpcg_of_clk_src_get()
168 if (idx >= hw_data->num) { in imx_lpcg_of_clk_src_get()
170 return ERR_PTR(-EINVAL); in imx_lpcg_of_clk_src_get()
[all …]
H A Dclk-imx8qxp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <linux/clk-provider.h>
15 #include "clk-scu.h"
17 #include <dt-bindings/firmware/imx/rsrc.h>
111 struct device_node *ccm_node = pdev->dev.of_node; in imx8qxp_clk_probe()
115 rsrc_table = of_device_get_match_data(&pdev->dev); in imx8qxp_clk_probe()
216 /* MIPI-LVDS SS */ in imx8qxp_clk_probe()
312 { .compatible = "fsl,scu-clk", },
313 { .compatible = "fsl,imx8dxl-clk", &imx_clk_scu_rsrc_imx8dxl, },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dfsl,imx8qxp-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
23 pattern: "^syscon@[0-9a-f]+$"
27 - enum:
28 - fsl,imx8qxp-mipi-lvds-csr
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
35 - $ref: simple-pm-bus.yaml#
37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8dx.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "fsl-imx8-ca35.dtsi"
8 #include <dt-bindings/soc/imx_rsrc.h>
9 #include <dt-bindings/soc/imx8_pd.h>
10 #include <dt-bindings/clock/imx8qxp-clock.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "fsl,imx8dx", "fsl,imx8qxp";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
[all …]
/openbmc/u-boot/drivers/misc/imx8/
H A Dscu.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <dm/device-internal.h>
29 struct udevice *clk; member
46 clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK | in mu_hal_init()
59 ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); in mu_hal_sendmsg()
62 return -ETIMEDOUT; in mu_hal_sendmsg()
65 writel(msg, &base->tr[reg_index]); in mu_hal_sendmsg()
79 ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); in mu_hal_receivemsg()
82 return -ETIMEDOUT; in mu_hal_receivemsg()
85 *msg = readl(&base->rr[reg_index]); in mu_hal_receivemsg()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
41 - fsl,imx8qm-ldb
42 - fsl,imx8qxp-ldb
44 "#address-cells":
47 "#size-cells":
52 - description: pixel clock
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,asrc.txt11 - compatible : Compatible list, should contain one of the following
13 "fsl,imx35-asrc",
14 "fsl,imx53-asrc",
15 "fsl,imx8qm-asrc",
16 "fsl,imx8qxp-asrc",
18 - reg : Offset and length of the register set for the device.
20 - interrupts : Contains the spdif interrupt.
22 - dmas : Generic dma devicetree binding as described in
25 - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
27 - clocks : Contains an entry for each entry in clock-names.
[all …]
H A Dfsl,mqs.txt4 - compatible : Must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs"
5 "fsl,imx8qm-mqs", "fsl,imx8qxp-mqs", "fsl,imx93-mqs".
6 - clocks : A list of phandles + clock-specifiers, one for each entry in
7 clock-names
8 - clock-names : "mclk" - must required.
9 "core" - required if compatible is "fsl,imx8qm-mqs", it
11 - gpr : A phandle of General Purpose Registers in IOMUX Controller.
12 Required if compatible is "fsl,imx6sx-mqs".
14 Required if compatible is "fsl,imx8qm-mqs":
15 - power-domains: A phandle of PM domain provider node.
[all …]
/openbmc/u-boot/drivers/clk/imx/
H A Dclk-imx8.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/imx8qxp-clock.h>
13 #include <dt-bindings/soc/imx_rsrc.h>
45 static ulong imx8_clk_get_rate(struct clk *clk) in imx8_clk_get_rate() argument
52 debug("%s(#%lu)\n", __func__, clk->id); in imx8_clk_get_rate()
54 switch (clk->id) { in imx8_clk_get_rate()
119 if (clk->id < IMX8QXP_UART0_IPG_CLK || in imx8_clk_get_rate()
120 clk->id >= IMX8QXP_CLK_END) { in imx8_clk_get_rate()
121 printf("%s(Invalid clk ID #%lu)\n", in imx8_clk_get_rate()
[all …]

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