| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-sp7021-intc.c | 81 static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value) in sp_intc_assign_bit() argument
87 offset = (hwirq / 32) * 4; in sp_intc_assign_bit()
93 mask |= BIT(hwirq % 32); in sp_intc_assign_bit()
95 mask &= ~BIT(hwirq % 32); in sp_intc_assign_bit()
102 u32 hwirq = d->hwirq; in sp_intc_ack_irq() local
104 if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND in sp_intc_ack_irq()
105 sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW)); in sp_intc_ack_irq()
106 ASSIGN_STATE(hwirq, _IS_ACTIVE, true); in sp_intc_ack_irq()
109 sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1); in sp_intc_ack_irq()
114 sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0); in sp_intc_mask_irq()
[all …]
|
| H A D | irq-mchp-eic.c | 51 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
53 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
62 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
64 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
74 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
96 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
103 irq_set_irq_wake(eic->irqs[d->hwirq], on); in mchp_eic_irq_set_wake()
105 eic->wakeup_source |= BIT(d->hwirq); in mchp_eic_irq_set_wake()
107 eic->wakeup_source &= ~BIT(d->hwirq); in mchp_eic_irq_set_wake()
114 unsigned int hwirq; in mchp_eic_irq_suspend() local
[all …]
|
| H A D | irq-mmp.c | 71 int hwirq; in icu_mask_ack_irq() local
74 hwirq = d->irq - data->virq_base; in icu_mask_ack_irq()
76 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
79 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
83 && (hwirq == data->clr_mfp_hwirq)) in icu_mask_ack_irq()
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
95 int hwirq; in icu_mask_irq() local
98 hwirq = d->irq - data->virq_base; in icu_mask_irq()
100 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
103 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
[all …]
|
| H A D | irq-mvebu-sei.c | 59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
61 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
74 reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_mask_irq()
82 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq()
88 reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_unmask_irq()
144 msg->data = data->hwirq + sei->caps->cp_range.first; in mvebu_sei_cp_compose_msi_msg()
199 unsigned long *hwirq, in mvebu_sei_ap_translate() argument
202 *hwirq = fwspec->param[0]; in mvebu_sei_ap_translate()
213 unsigned long hwirq; in mvebu_sei_ap_alloc() local
[all …]
|
| H A D | irq-sifive-plic.c | 93 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) in __plic_toggle() argument
95 u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32); in __plic_toggle()
96 u32 hwirq_mask = 1 << (hwirq % 32); in __plic_toggle()
104 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) in plic_toggle() argument
107 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle()
119 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle()
127 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_unmask()
134 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_mask()
153 plic_toggle(handler, d->hwirq, 1); in plic_irq_eoi()
154 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); in plic_irq_eoi()
[all …]
|
| H A D | irq-pruss-intc.c | 173 * @hwirq: the system event number
178 static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_map() argument
186 intc->event_channel[hwirq].ref_count++; in pruss_intc_map()
188 ch = intc->event_channel[hwirq].value; in pruss_intc_map()
191 pruss_intc_update_cmr(intc, hwirq, ch); in pruss_intc_map()
193 reg_idx = hwirq / 32; in pruss_intc_map()
194 val = BIT(hwirq % 32); in pruss_intc_map()
208 hwirq, ch, host); in pruss_intc_map()
216 * @hwirq: the system event number
222 static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_unmap() argument
[all …]
|
| H A D | irq-ls-extirq.c | 57 irq_hw_number_t hwirq = data->hwirq; in ls_extirq_set_type() local
61 mask = 1U << (31 - hwirq); in ls_extirq_set_type()
63 mask = 1U << hwirq; in ls_extirq_set_type()
104 irq_hw_number_t hwirq; in ls_extirq_domain_alloc() local
109 hwirq = fwspec->param[0]; in ls_extirq_domain_alloc()
110 if (hwirq >= priv->nirq) in ls_extirq_domain_alloc()
113 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip, in ls_extirq_domain_alloc()
116 return irq_domain_alloc_irqs_parent(domain, virq, 1, &priv->map[hwirq]); in ls_extirq_domain_alloc()
141 u32 hwirq, intsize, j; in ls_extirq_parse_map() local
145 hwirq = be32_to_cpup(map); in ls_extirq_parse_map()
[all …]
|
| H A D | irq-partition-percpu.c | 26 unsigned int cpu, unsigned int hwirq) in partition_check_cpu() argument
28 return cpumask_test_cpu(cpu, &part->parts[hwirq].mask); in partition_check_cpu()
37 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_mask()
48 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_unmask()
61 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_set_irqchip_state()
76 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_get_irqchip_state()
101 seq_printf(p, " %5s-%lu", chip->name, data->hwirq); in partition_irq_print_chip()
118 int hwirq; in partition_handle_irq() local
122 for_each_set_bit(hwirq, part->bitmap, part->nr_parts) { in partition_handle_irq()
123 if (partition_check_cpu(part, cpu, hwirq)) in partition_handle_irq()
[all …]
|
| H A D | irq-or1k-pic.c | 28 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_mask()
33 mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq)); in or1k_pic_unmask()
38 mtspr(SPR_PICSR, (1UL << data->hwirq)); in or1k_pic_ack()
43 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_mask_ack()
44 mtspr(SPR_PICSR, (1UL << data->hwirq)); in or1k_pic_mask_ack()
55 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_ack()
60 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_mask_ack()
61 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_mask_ack()
102 int hwirq; in pic_get_irq() local
104 hwirq = ffs(mfspr(SPR_PICSR) >> first); in pic_get_irq()
[all …]
|
| H A D | irq-ti-sci-inta.c | 30 #define HWIRQ_TO_DEVID(hwirq) (((hwirq) >> (TI_SCI_DEV_ID_SHIFT)) & \ argument
32 #define HWIRQ_TO_IRQID(hwirq) ((hwirq) & (TI_SCI_IRQ_ID_MASK)) argument
47 * hwirq and vint bit.
49 * @hwirq: Hwirq of the incoming interrupt
54 u32 hwirq; member
118 static u16 ti_sci_inta_get_dev_id(struct ti_sci_inta_irq_domain *inta, u32 hwirq) in ti_sci_inta_get_dev_id() argument
120 u16 dev_id = HWIRQ_TO_DEVID(hwirq); in ti_sci_inta_get_dev_id()
163 generic_handle_domain_irq(domain, vint_desc->events[bit].hwirq); in ti_sci_inta_irq_handler()
169 * ti_sci_inta_xlate_irq() - Translate hwirq to parent's hwirq.
275 * @hwirq: hwirq of the input event
[all …]
|
| H A D | irq-loongson-pch-pic.c | 83 pch_pic_bitset(priv, PCH_PIC_MASK, d->hwirq); in pch_pic_mask_irq()
91 writel(BIT(PIC_REG_BIT(d->hwirq)), in pch_pic_unmask_irq()
92 priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4); in pch_pic_unmask_irq()
95 pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq); in pch_pic_unmask_irq()
105 pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq); in pch_pic_set_type()
106 pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq); in pch_pic_set_type()
110 pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq); in pch_pic_set_type()
111 pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq); in pch_pic_set_type()
115 pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq); in pch_pic_set_type()
116 pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq); in pch_pic_set_type()
[all …]
|
| H A D | irq-sni-exiu.c | 44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
58 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
89 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_enable()
91 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_enable()
103 val |= BIT(d->hwirq); in exiu_irq_set_type()
105 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
110 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
113 val |= BIT(d->hwirq); in exiu_irq_set_type()
[all …]
|
| H A D | irq-riscv-intc.c | 44 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
49 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
55 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
59 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_mask()
61 if (d->hwirq < ANDES_SLI_CAUSE_BASE) in andes_intc_irq_mask()
69 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_unmask()
71 if (d->hwirq < ANDES_SLI_CAUSE_BASE) in andes_intc_irq_unmask()
108 irq_hw_number_t hwirq) in riscv_intc_domain_map() argument
113 irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq, in riscv_intc_domain_map()
124 irq_hw_number_t hwirq; in riscv_intc_domain_alloc() local
[all …]
|
| H A D | irq-mvebu-odmi.c | 56 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME)) in odmi_compose_msi_msg()
59 odmi = &odmis[d->hwirq >> NODMIS_SHIFT]; in odmi_compose_msi_msg()
60 odmin = d->hwirq & NODMIS_MASK; in odmi_compose_msi_msg()
84 unsigned int hwirq, odmin; in odmi_irq_domain_alloc() local
88 hwirq = find_first_zero_bit(odmis_bm, NODMIS_PER_FRAME * odmis_count); in odmi_irq_domain_alloc()
89 if (hwirq >= NODMIS_PER_FRAME * odmis_count) { in odmi_irq_domain_alloc()
94 __set_bit(hwirq, odmis_bm); in odmi_irq_domain_alloc()
97 odmi = &odmis[hwirq >> NODMIS_SHIFT]; in odmi_irq_domain_alloc()
98 odmin = hwirq & NODMIS_MASK; in odmi_irq_domain_alloc()
119 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, in odmi_irq_domain_alloc()
[all …]
|
| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | mpic_u3msi.c | 61 static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_ht_magic_addr() argument
75 static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_u4_magic_addr() argument
97 return 0xf8004000 | (hwirq << 4); in find_u4_magic_addr()
105 irq_hw_number_t hwirq; in u3msi_teardown_msi_irqs() local
108 hwirq = virq_to_hw(entry->irq); in u3msi_teardown_msi_irqs()
112 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1); in u3msi_teardown_msi_irqs()
122 int hwirq; in u3msi_setup_msi_irqs() local
136 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1); in u3msi_setup_msi_irqs()
137 if (hwirq < 0) { in u3msi_setup_msi_irqs()
138 pr_debug("u3msi: failed allocating hwirq\n"); in u3msi_setup_msi_irqs()
[all …]
|
| /openbmc/linux/arch/powerpc/platforms/powernv/ |
| H A D | pci-cxl.c | 43 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); in pnv_cxl_alloc_hwirqs() local
45 if (hwirq < 0) { in pnv_cxl_alloc_hwirqs()
50 return phb->msi_base + hwirq; in pnv_cxl_alloc_hwirqs()
54 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) in pnv_cxl_release_hwirqs() argument
59 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); in pnv_cxl_release_hwirqs()
68 int i, hwirq; in pnv_cxl_release_hwirq_ranges() local
76 hwirq = irqs->offset[i] - phb->msi_base; in pnv_cxl_release_hwirq_ranges()
77 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, in pnv_cxl_release_hwirq_ranges()
88 int i, hwirq, try; in pnv_cxl_alloc_hwirq_ranges() local
96 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); in pnv_cxl_alloc_hwirq_ranges()
[all …]
|
| /openbmc/linux/arch/powerpc/platforms/85xx/ |
| H A D | socrates_fpga_pic.c | 108 unsigned int irq_line, hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_ack() local
111 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_ack()
115 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_ack()
123 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask() local
127 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask()
131 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask()
139 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask_ack() local
143 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask_ack()
147 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask_ack()
148 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_mask_ack()
[all …]
|
| /openbmc/linux/Documentation/core-api/irq/ |
| H A D | irq-domain.rst | 29 the controller-local IRQ (hwirq) number into the Linux IRQ number
32 The irq_domain library adds mapping between hwirq and IRQ numbers on
38 structure to hwirq numbers (Device Tree and ACPI GSI so far), and can
51 between hwirq and IRQ numbers. Mappings are added to the irq_domain
53 hwirq number as arguments. If a mapping for the hwirq doesn't already
55 the hwirq, and call the .map() callback so the driver can perform any
62 for a given domain and hwirq number, and NULL if there was no
65 hwirq number, and 0 if there was no mapping
69 domain and a hwirq number
79 needs to know the associated hwirq number (such as in the irq_chip
[all …]
|
| /openbmc/linux/arch/powerpc/platforms/pasemi/ |
| H A D | msi.c | 61 irq_hw_number_t hwirq; in pasemi_msi_teardown_msi_irqs() local
66 hwirq = virq_to_hw(entry->irq); in pasemi_msi_teardown_msi_irqs()
70 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK); in pasemi_msi_teardown_msi_irqs()
79 int hwirq; in pasemi_msi_setup_msi_irqs() local
95 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, in pasemi_msi_setup_msi_irqs()
97 if (hwirq < 0) { in pasemi_msi_setup_msi_irqs()
98 pr_debug("pasemi_msi: failed allocating hwirq\n"); in pasemi_msi_setup_msi_irqs()
99 return hwirq; in pasemi_msi_setup_msi_irqs()
102 virq = irq_create_mapping(msi_mpic->irqhost, hwirq); in pasemi_msi_setup_msi_irqs()
104 pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n", in pasemi_msi_setup_msi_irqs()
[all …]
|
| /openbmc/linux/kernel/irq/ |
| H A D | irqdomain.c | 386 * @first_hwirq: first hwirq number to use for the translation. Should normally
506 irq_hw_number_t hwirq) in irq_domain_clear_mapping() argument
513 if (hwirq < domain->revmap_size) in irq_domain_clear_mapping()
514 rcu_assign_pointer(domain->revmap[hwirq], NULL); in irq_domain_clear_mapping()
516 radix_tree_delete(&domain->revmap_tree, hwirq); in irq_domain_clear_mapping()
520 irq_hw_number_t hwirq, in irq_domain_set_mapping() argument
532 if (hwirq < domain->revmap_size) in irq_domain_set_mapping()
533 rcu_assign_pointer(domain->revmap[hwirq], irq_data); in irq_domain_set_mapping()
535 radix_tree_insert(&domain->revmap_tree, hwirq, irq_data); in irq_domain_set_mapping()
541 irq_hw_number_t hwirq; in irq_domain_disassociate() local
[all …]
|
| /openbmc/linux/drivers/pinctrl/mediatek/ |
| H A D | mtk-eint.c | 101 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) in mtk_eint_flip_edge() argument
105 u32 mask = BIT(hwirq & 0x1f); in mtk_eint_flip_edge()
106 u32 port = (hwirq >> 5) & eint->hw->port_mask; in mtk_eint_flip_edge()
109 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); in mtk_eint_flip_edge()
120 hwirq); in mtk_eint_flip_edge()
129 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_mask()
130 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_mask()
133 eint->cur_mask[d->hwirq >> 5] &= ~mask; in mtk_eint_mask()
141 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_unmask()
142 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_unmask()
[all …]
|
| /openbmc/linux/drivers/pci/controller/ |
| H A D | pcie-iproc-msi.c | 146 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_group() argument
148 return (hwirq % msi->nr_irqs); in hwirq_to_group()
152 unsigned long hwirq) in iproc_msi_addr_offset() argument
155 return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE; in iproc_msi_addr_offset()
157 return hwirq_to_group(msi, hwirq) * sizeof(u32); in iproc_msi_addr_offset()
195 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_cpu() argument
197 return (hwirq % msi->nr_cpus); in hwirq_to_cpu()
201 unsigned long hwirq) in hwirq_to_canonical_hwirq()
203 return (hwirq - hwirq_to_cpu(msi, hwirq)); in hwirq_to_canonical_hwirq()
214 curr_cpu = hwirq_to_cpu(msi, data->hwirq); in iproc_msi_irq_set_affinity()
[all …]
|
| /openbmc/linux/arch/arm/mach-imx/ |
| H A D | gpc.c | 91 unsigned int idx = d->hwirq / 32; in imx_gpc_irq_set_wake()
94 mask = 1 << d->hwirq % 32; in imx_gpc_irq_set_wake()
125 void imx_gpc_hwirq_unmask(unsigned int hwirq) in imx_gpc_hwirq_unmask() argument
130 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_unmask()
132 val &= ~(1 << hwirq % 32); in imx_gpc_hwirq_unmask()
136 void imx_gpc_hwirq_mask(unsigned int hwirq) in imx_gpc_hwirq_mask() argument
141 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_mask()
143 val |= 1 << (hwirq % 32); in imx_gpc_hwirq_mask()
149 imx_gpc_hwirq_unmask(d->hwirq); in imx_gpc_irq_unmask()
155 imx_gpc_hwirq_mask(d->hwirq); in imx_gpc_irq_mask()
[all …]
|
| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-hlwd.c | 66 int hwirq; in hlwd_gpio_irqhandler() local
101 for_each_set_bit(hwirq, &pending, 32) in hlwd_gpio_irqhandler()
102 generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq); in hlwd_gpio_irqhandler()
112 iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG); in hlwd_gpio_irq_ack()
124 mask &= ~BIT(data->hwirq); in hlwd_gpio_irq_mask()
140 mask |= BIT(data->hwirq); in hlwd_gpio_irq_unmask()
151 static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq, in hlwd_gpio_irq_setup_emulation() argument
158 state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq); in hlwd_gpio_irq_setup_emulation()
159 level &= ~BIT(hwirq); in hlwd_gpio_irq_setup_emulation()
160 level |= state ^ BIT(hwirq); in hlwd_gpio_irq_setup_emulation()
[all …]
|
| /openbmc/linux/drivers/misc/cxl/ |
| H A D | irq.c | 174 irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq)); in cxl_irq_afu() local
192 irq_off = hwirq - ctx->irqs.offset[r]; in cxl_irq_afu()
201 WARN(1, "Received AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n", in cxl_irq_afu()
202 ctx->pe, irq, hwirq); in cxl_irq_afu()
206 trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq); in cxl_irq_afu()
207 pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n", in cxl_irq_afu()
208 afu_irq, ctx->pe, irq, hwirq); in cxl_irq_afu()
224 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, in cxl_map_irq() argument
231 virq = irq_create_mapping(NULL, hwirq); in cxl_map_irq()
238 cxl_ops->setup_irq(adapter, hwirq, virq); in cxl_map_irq()
[all …]
|