44 	csr_clear(CSR_IE, BIT(d->hwirq));  in riscv_intc_irq_mask()
49 	csr_set(CSR_IE, BIT(d->hwirq));  in riscv_intc_irq_unmask()
55 	 * Andes specific S-mode local interrupt causes (hwirq)  in andes_intc_irq_mask()
59 	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);  in andes_intc_irq_mask()
61 	if (d->hwirq < ANDES_SLI_CAUSE_BASE)  in andes_intc_irq_mask()
69 	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);  in andes_intc_irq_unmask()
71 	if (d->hwirq < ANDES_SLI_CAUSE_BASE)  in andes_intc_irq_unmask()
108 				 irq_hw_number_t hwirq)  in riscv_intc_domain_map()  argument
113 	irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,  in riscv_intc_domain_map()
124 	irq_hw_number_t hwirq;  in riscv_intc_domain_alloc()  local
128 	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);  in riscv_intc_domain_alloc()
133 	 * Only allow hwirq for which we have corresponding standard or  in riscv_intc_domain_alloc()
136 	if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||  in riscv_intc_domain_alloc()
137 	    (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))  in riscv_intc_domain_alloc()
141 		ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);  in riscv_intc_domain_alloc()