81 static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value)  in sp_intc_assign_bit()  argument
87 	offset = (hwirq / 32) * 4;  in sp_intc_assign_bit()
93 		mask |= BIT(hwirq % 32);  in sp_intc_assign_bit()
95 		mask &= ~BIT(hwirq % 32);  in sp_intc_assign_bit()
102 	u32 hwirq = d->hwirq;  in sp_intc_ack_irq()  local
104 	if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND  in sp_intc_ack_irq()
105 		sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW));  in sp_intc_ack_irq()
106 		ASSIGN_STATE(hwirq, _IS_ACTIVE, true);  in sp_intc_ack_irq()
109 	sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1);  in sp_intc_ack_irq()
114 	sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0);  in sp_intc_mask_irq()
119 	sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 1);  in sp_intc_unmask_irq()
124 	u32 hwirq = d->hwirq;  in sp_intc_set_type()  local
130 	if (unlikely(IS_GPIO_INT(hwirq) && is_edge)) { // WORKAROUND  in sp_intc_set_type()
132 		ASSIGN_STATE(hwirq, _IS_EDGE, is_edge);  in sp_intc_set_type()
133 		ASSIGN_STATE(hwirq, _IS_LOW, is_low);  in sp_intc_set_type()
134 		ASSIGN_STATE(hwirq, _IS_ACTIVE, false);  in sp_intc_set_type()
139 	sp_intc_assign_bit(hwirq, REG_INTR_TYPE, is_edge);  in sp_intc_set_type()
140 	sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, is_low);  in sp_intc_set_type()
171 	int hwirq;  in sp_intc_handle_ext_cascaded()  local
175 	while ((hwirq = sp_intc_get_ext_irq(ext_num)) >= 0) {  in sp_intc_handle_ext_cascaded()
176 		if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_ACTIVE))) { // WORKAROUND  in sp_intc_handle_ext_cascaded()
177 			ASSIGN_STATE(hwirq, _IS_ACTIVE, false);  in sp_intc_handle_ext_cascaded()
178 			sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, TEST_STATE(hwirq, _IS_LOW));  in sp_intc_handle_ext_cascaded()
180 			generic_handle_domain_irq(sp_intc.domain, hwirq);  in sp_intc_handle_ext_cascaded()
196 				  unsigned int irq, irq_hw_number_t hwirq)  in sp_intc_irq_domain_map()  argument