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/openbmc/linux/drivers/clk/samsung/
H A Dclk-s3c64xx.c163 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
191 DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
197 GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
198 GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
199 GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
200 GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
201 GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
202 GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
203 GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
204 GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
[all …]
H A Dclk-s5pv210-audss.c70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
86 hclk = devm_clk_get(&pdev->dev, "hclk"); in s5pv210_audss_clk_probe()
87 if (IS_ERR(hclk)) { in s5pv210_audss_clk_probe()
88 dev_err(&pdev->dev, "failed to get hclk clock\n"); in s5pv210_audss_clk_probe()
89 return PTR_ERR(hclk); in s5pv210_audss_clk_probe()
140 hclk_p = __clk_get_name(hclk); in s5pv210_audss_clk_probe()
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx1.c22 static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
52 clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4); in mx1_clocks_init_dt()
58 clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); in mx1_clocks_init_dt()
59 clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); in mx1_clocks_init_dt()
60 clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); in mx1_clocks_init_dt()
61 clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); in mx1_clocks_init_dt()
62 clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); in mx1_clocks_init_dt()
63 clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); in mx1_clocks_init_dt()
/openbmc/linux/drivers/clk/
H A Dclk-stm32h7.c73 "hclk", "pll1_q", "pll2_r", "per_ck" };
76 "hclk", "pll1_q", "pll2_r", "per_ck" };
517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre", in register_core_and_bus_clocks()
527 hws[PCLK3] = clk_hw_register_divider_table(NULL, "pclk3", "hclk", 0, in register_core_and_bus_clocks()
533 hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0, in register_core_and_bus_clocks()
542 hws[PCLK2] = clk_hw_register_divider_table(NULL, "pclk2", "hclk", 0, in register_core_and_bus_clocks()
551 hws[PCLK4] = clk_hw_register_divider_table(NULL, "pclk4", "hclk", 0, in register_core_and_bus_clocks()
998 PER_CLK(RCC_AHB3ENR, 31, "d1sram1", "hclk"),
999 PER_CLK(RCC_AHB3ENR, 30, "itcm", "hclk"),
1000 PER_CLK(RCC_AHB3ENR, 29, "dtcm2", "hclk"),
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml191 - description: HCLK which used for host
197 - const: hclk
211 - description: HCLK which used for host
218 - const: hclk
244 - description: HCLK which used for host
252 - const: hclk
269 - description: HCLK which used for host
275 - const: hclk
289 - description: HCLK which used for host
298 - const: hclk
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/openbmc/linux/drivers/net/ethernet/cadence/
H A Dmacb_pci.c69 plat_data.hclk = clk_register_fixed_rate(&pdev->dev, "hclk", NULL, 0, in macb_probe()
71 if (IS_ERR(plat_data.hclk)) { in macb_probe()
72 err = PTR_ERR(plat_data.hclk); in macb_probe()
100 clk_unregister(plat_data.hclk); in macb_probe()
115 clk_unregister(plat_data->hclk); in macb_remove()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dlowlevel_init.S10 * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
21 /* Set ARM, HCLK, PCLK dividers for normal mode */
26 /* Start HCLK PLL for 208 MHz */
31 /* wait for HCLK PLL to lock */
/openbmc/linux/sound/soc/rockchip/
H A Drockchip_spdif.c37 struct clk *hclk; member
73 clk_disable_unprepare(spdif->hclk); in rk_spdif_runtime_suspend()
89 ret = clk_prepare_enable(spdif->hclk); in rk_spdif_runtime_resume()
92 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret); in rk_spdif_runtime_resume()
102 clk_disable_unprepare(spdif->hclk); in rk_spdif_runtime_resume()
314 spdif->hclk = devm_clk_get(&pdev->dev, "hclk"); in rk_spdif_probe()
315 if (IS_ERR(spdif->hclk)) in rk_spdif_probe()
316 return PTR_ERR(spdif->hclk); in rk_spdif_probe()
326 spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs, in rk_spdif_probe()
H A Drockchip_pdm.c34 struct clk *hclk; member
416 clk_disable_unprepare(pdm->hclk); in rockchip_pdm_runtime_suspend()
432 ret = clk_prepare_enable(pdm->hclk); in rockchip_pdm_runtime_resume()
615 pdm->hclk = devm_clk_get(&pdev->dev, "pdm_hclk"); in rockchip_pdm_probe()
616 if (IS_ERR(pdm->hclk)) in rockchip_pdm_probe()
617 return PTR_ERR(pdm->hclk); in rockchip_pdm_probe()
619 ret = clk_prepare_enable(pdm->hclk); in rockchip_pdm_probe()
659 clk_disable_unprepare(pdm->hclk); in rockchip_pdm_probe()
673 clk_disable_unprepare(pdm->hclk); in rockchip_pdm_remove()
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Datmel-usb.txt13 "hclk" for the host clock
25 clock-names = "ohci_clk", "hclk", "uhpck";
67 "hclk" for the AHB clock
78 clock-names = "pclk", "hclk";
98 "hclk" for the host clock
123 clock-names = "hclk", "pclk";
/openbmc/linux/drivers/char/hw_random/
H A Djh7110-trng.c98 struct clk *hclk; member
241 clk_disable_unprepare(trng->hclk); in starfive_trng_cleanup()
306 trng->hclk = devm_clk_get(&pdev->dev, "hclk"); in starfive_trng_probe()
307 if (IS_ERR(trng->hclk)) in starfive_trng_probe()
308 return dev_err_probe(&pdev->dev, PTR_ERR(trng->hclk), in starfive_trng_probe()
321 clk_prepare_enable(trng->hclk); in starfive_trng_probe()
344 clk_disable_unprepare(trng->hclk); in starfive_trng_probe()
356 clk_disable_unprepare(trng->hclk); in starfive_trng_suspend()
366 clk_prepare_enable(trng->hclk); in starfive_trng_resume()
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
227 hclk: hclk@0 { label
229 compatible = "st,nomadik-hclk-clock";
232 /* The PCLK domain uses HCLK right off */
238 clocks = <&hclk>;
302 clocks = <&hclk>;
308 clocks = <&hclk>;
314 clocks = <&hclk>;
320 clocks = <&hclk>;
326 clocks = <&hclk>;
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/openbmc/linux/arch/arm/mach-mv78xx0/
H A Dcommon.c47 int hclk; in get_hclk() local
50 * HCLK tick rate is configured by DEV_D[7:5] pins. in get_hclk()
54 hclk = 166666667; in get_hclk()
57 hclk = 200000000; in get_hclk()
60 hclk = 266666667; in get_hclk()
63 hclk = 333333333; in get_hclk()
66 hclk = 400000000; in get_hclk()
69 panic("unknown HCLK PLL setting: %.8x\n", in get_hclk()
73 return hclk; in get_hclk()
76 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) in get_pclk_l2clk() argument
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dfsmc-nand.txt19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,nomadik.txt34 HCLK nodes: these represent the clock gates on individual
35 lines from the HCLK clock tree and the gate for individual
38 Requires properties for the HCLK nodes:
39 - compatible: must be "st,nomadik-hclk-clock"
/openbmc/linux/drivers/crypto/starfive/
H A Djh7110-cryp.c147 cryp->hclk = devm_clk_get(&pdev->dev, "hclk"); in starfive_cryp_probe()
148 if (IS_ERR(cryp->hclk)) in starfive_cryp_probe()
149 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->hclk), in starfive_cryp_probe()
174 clk_prepare_enable(cryp->hclk); in starfive_cryp_probe()
226 clk_disable_unprepare(cryp->hclk); in starfive_cryp_probe()
256 clk_disable_unprepare(cryp->hclk); in starfive_cryp_remove()
/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dpm.c21 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
22 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
26 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
57 * HCLK PLL state is restored
/openbmc/u-boot/drivers/misc/
H A Dmxs_ocotp.c67 * be asserted only after a few HCLK cycles and if we were to in mxs_ocotp_read_bank_open()
151 /* Return the original HCLK clock speed. */ in mxs_ocotp_scale_hclk()
156 /* Scale the HCLK to 454/19 = 23.9 MHz . */ in mxs_ocotp_scale_hclk()
160 /* Scale the HCLK back to original frequency. */ in mxs_ocotp_scale_hclk()
201 puts("Failed scaling down the HCLK!\n"); in mxs_ocotp_write_fuse()
236 puts("Failed scaling up the HCLK!\n"); in mxs_ocotp_write_fuse()
/openbmc/linux/drivers/soc/qcom/
H A Dqcom_gsbi.c111 struct clk *hclk; member
181 gsbi->hclk = devm_clk_get_enabled(&pdev->dev, "iface"); in gsbi_probe()
182 if (IS_ERR(gsbi->hclk)) in gsbi_probe()
183 return PTR_ERR(gsbi->hclk); in gsbi_probe()
219 clk_disable_unprepare(gsbi->hclk); in gsbi_remove()
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.c46 struct clk *hclk; member
774 hdmi->hclk = devm_clk_get(dev, "hclk"); in rk3066_hdmi_bind()
775 if (IS_ERR(hdmi->hclk)) { in rk3066_hdmi_bind()
776 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n"); in rk3066_hdmi_bind()
777 return PTR_ERR(hdmi->hclk); in rk3066_hdmi_bind()
780 ret = clk_prepare_enable(hdmi->hclk); in rk3066_hdmi_bind()
782 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret); in rk3066_hdmi_bind()
794 /* internal hclk = hdmi_hclk / 25 */ in rk3066_hdmi_bind()
834 clk_disable_unprepare(hdmi->hclk); in rk3066_hdmi_bind()
848 clk_disable_unprepare(hdmi->hclk); in rk3066_hdmi_unbind()
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c1143 u32 tmp, hclk; in get_target_freq() local
1147 hclk = 84; in get_target_freq()
1160 hclk = 150; in get_target_freq()
1166 hclk = 165; in get_target_freq()
1170 hclk = 180; in get_target_freq()
1177 hclk = 200; in get_target_freq()
1182 hclk = 222; in get_target_freq()
1188 hclk = 250; in get_target_freq()
1194 hclk = 267; in get_target_freq()
1200 hclk = 300; in get_target_freq()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml80 - enum: [ ether_clk, hclk, pclk ]
81 - enum: [ hclk, pclk ]
182 clock-names = "pclk", "hclk", "tx_clk";
210 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/openbmc/u-boot/drivers/spi/
H A Daspeed_spi.c302 /* HCLK/1 .. HCLK/16 */ in aspeed_g6_spi_hclk_divisor()
326 debug("hclk=%d required=%d h_div %d, divisor is %d (mask %x) speed=%d\n", in aspeed_g6_spi_hclk_divisor()
337 /* HCLK/1 .. HCLK/16 */ in aspeed_spi_hclk_divisor()
348 debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", in aspeed_spi_hclk_divisor()
505 /* HCLK/5 .. HCLK/1 */ in aspeed_spi_timing_calibration()
541 /* Compute reference checksum at lowest freq HCLK/16 */ in aspeed_spi_timing_calibration()
547 * HCLK division. in aspeed_spi_timing_calibration()
555 /* from HCLK/2 to HCLK/5 */ in aspeed_spi_timing_calibration()
574 debug("HCLK/%d, %d HCLK cycle, %d delay_ns : %s\n", in aspeed_spi_timing_calibration()
621 /* Compute reference checksum at lowest freq HCLK/16 */ in aspeed_spi_timing_calibration()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-sun4i.c80 struct clk *hclk; member
393 ret = clk_prepare_enable(sspi->hclk); in sun4i_spi_runtime_resume()
411 clk_disable_unprepare(sspi->hclk); in sun4i_spi_runtime_resume()
422 clk_disable_unprepare(sspi->hclk); in sun4i_spi_runtime_suspend()
473 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); in sun4i_spi_probe()
474 if (IS_ERR(sspi->hclk)) { in sun4i_spi_probe()
476 ret = PTR_ERR(sspi->hclk); in sun4i_spi_probe()
/openbmc/linux/Documentation/devicetree/bindings/rng/
H A Dstarfive,jh7110-trng.yaml26 - const: hclk
51 clock-names = "hclk", "ahb";

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