302 	/* HCLK/1 ..	HCLK/16 */  in aspeed_g6_spi_hclk_divisor()
326 	debug("hclk=%d required=%d h_div %d, divisor is %d (mask %x) speed=%d\n",  in aspeed_g6_spi_hclk_divisor()
337 	/* HCLK/1 ..	HCLK/16 */  in aspeed_spi_hclk_divisor()
348 	debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n",  in aspeed_spi_hclk_divisor()
505 	/* HCLK/5 .. HCLK/1 */  in aspeed_spi_timing_calibration()
541 		/* Compute reference checksum at lowest freq HCLK/16 */  in aspeed_spi_timing_calibration()
547 		 * HCLK division.  in aspeed_spi_timing_calibration()
555 		/* from HCLK/2 to HCLK/5 */  in aspeed_spi_timing_calibration()
574 					debug("HCLK/%d, %d HCLK cycle, %d delay_ns : %s\n",  in aspeed_spi_timing_calibration()
621 		/* Compute reference checksum at lowest freq HCLK/16 */  in aspeed_spi_timing_calibration()
635 			/* Increase HCLK cycles until read succeeds */  in aspeed_spi_timing_calibration()
642 				debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n",  in aspeed_spi_timing_calibration()
645 				/* Try again with more HCLK cycles */  in aspeed_spi_timing_calibration()
654 				debug(" HCLK/%d,  no DI delay, %d HCLK cycle : %s\n",  in aspeed_spi_timing_calibration()
1853 	struct clk hclk;  in aspeed_spi_probe()  local
1869 	ret = clk_get_by_index(bus, 0, &hclk);  in aspeed_spi_probe()
1875 	priv->hclk_rate = clk_get_rate(&hclk);  in aspeed_spi_probe()
1876 	clk_free(&hclk);  in aspeed_spi_probe()