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/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
32 reg-names:
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H A Dahci-platform.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
14 It allows to enable each port independently when dealing with multiple
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
26 - brcm,iproc-ahci
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H A Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
26 - $ref: snps,dwc-ahci-common.yaml#
31 - description: Synopsys AHCI SATA-compatible devices
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H A Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
30 - enum:
31 - rockchip,rk3568-dwc-ahci
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/openbmc/qemu/hw/ide/
H A Dahci.c28 #include "hw/qdev-properties.h"
31 #include "qemu/error-report.h"
33 #include "qemu/main-loop.h"
35 #include "sysemu/block-backend.h"
38 #include "hw/ide/ahci-pci.h"
39 #include "hw/ide/ahci-sysbus.h"
40 #include "ahci-internal.h"
41 #include "ide-internal.h"
45 static void check_cmd(AHCIState *s, int port);
46 static void handle_cmd(AHCIState *s, int port, uint8_t slot);
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H A Dich.c21 * lspci dump of a ICH-9 real device
23 …: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (…
24 …* Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [80…
25 …* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- Fast…
26 …* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR…
34 * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
35 * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
38 * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
39 * Status: D0 PME-Enable- DSel=0 DScale=0 PME-
40 * Capabilities: [a8] SATA HBA <?>
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H A Dahci-internal.h29 #include "ide-internal.h"
60 AHCI_HOST_REG_CAP = 0, /* CAP: host capabilities */
75 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
83 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
85 #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */
87 /* registers for each SATA port */
95 AHCI_PORT_REG_CMD = 6, /* PxCMD: port command */
105 AHCI_PORT_REG_FIS_CTL = 16, /* PxFBS: Port multiplier switching ctl */
115 /* Port interrupt bit descriptors */
146 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
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/openbmc/qemu/tests/qtest/
H A Dahci-test.c29 #include "libqos/libqos-pc.h"
31 #include "libqos/pci-pc.h"
34 #include "qemu/host-utils.h"
52 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
72 while (bytes--) { in string_bswap16()
88 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID); in verify_state()
89 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint); in verify_state()
92 if (!ahci->enabled) { in verify_state()
96 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); in verify_state()
99 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap); in verify_state()
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/openbmc/linux/drivers/s390/scsi/
H A Dzfcp_dbf.c1 // SPDX-License-Identifier: GPL-2.0
36 return sizeof(struct zfcp_dbf_pay) + offset - ZFCP_DBF_PAY_MAX_REC; in zfcp_dbf_plen()
43 struct zfcp_dbf_pay *pl = &dbf->pay_buf; in zfcp_dbf_pl_write()
46 spin_lock(&dbf->pay_lock); in zfcp_dbf_pl_write()
48 pl->fsf_req_id = req_id; in zfcp_dbf_pl_write()
49 memcpy(pl->area, area, ZFCP_DBF_TAG_LEN); in zfcp_dbf_pl_write()
53 (u16) (length - offset)); in zfcp_dbf_pl_write()
54 memcpy(pl->data, data + offset, rec_length); in zfcp_dbf_pl_write()
55 debug_event(dbf->pay, 1, pl, zfcp_dbf_plen(rec_length)); in zfcp_dbf_pl_write()
58 pl->counter++; in zfcp_dbf_pl_write()
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/openbmc/linux/drivers/ata/
H A Dlibahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2004-2005 Red Hat, Inc.
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
52 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
56 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
58 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
62 rc = phy_power_on(hpriv->phys[i]); in ahci_platform_enable_phys()
64 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
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H A Dlibahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libahci.c - Common AHCI SATA low-level routines
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
27 #include <linux/dma-mapping.h>
236 * ahci_rpm_get_port - Make sure the port is powered on
237 * @ap: Port to power on
245 return pm_runtime_get_sync(ap->dev); in ahci_rpm_get_port()
249 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
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H A Dacard-ahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * acard-ahci.c - ACard AHCI SATA support
7 * Please ALWAYS copy linux-ide@vger.kernel.org
13 * as Documentation/driver-api/libata.rst
26 #include <linux/dma-mapping.h>
35 #define DRV_NAME "acard-ahci"
70 AHCI_SHT("acard-ahci"),
115 struct ahci_host_priv *hpriv = host->private_data; in acard_ahci_pci_device_suspend()
116 void __iomem *mmio = hpriv->mmio; in acard_ahci_pci_device_suspend()
120 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { in acard_ahci_pci_device_suspend()
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H A Dsata_highbank.c1 // SPDX-License-Identifier: GPL-2.0-only
53 /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
88 static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, in sgpio_bit_shift() argument
91 return 1 << (3 * pdata->port_to_sgpio[port] + shift); in sgpio_bit_shift()
94 static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state) in ecx_parse_sgpio() argument
97 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
100 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
103 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
106 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
109 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
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H A Dahci_dwc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #define DRV_NAME "ahci-dwc"
95 /* Baikal-T1 AHCI SATA specific registers */
127 struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; in ahci_bt1_init()
134 dev_err(&dpriv->pdev->dev, "No system clocks specified\n"); in ahci_bt1_init()
135 return -EINVAL; in ahci_bt1_init()
145 dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n"); in ahci_bt1_init()
151 dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n"); in ahci_bt1_init()
163 dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL); in ahci_dwc_get_resources()
165 return ERR_PTR(-ENOMEM); in ahci_dwc_get_resources()
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H A Dahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
25 #include <linux/dma-mapping.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
265 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
275 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
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/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dsata.c1 // SPDX-License-Identifier: GPL-2.0
27 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
28 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
46 int port; in broadwell_sata_init() local
54 /* for AHCI, Port Enable is managed in memory mapped space */ in broadwell_sata_init()
57 reg16 |= 0x8000 | plat->port_map; in broadwell_sata_init()
75 reg32 |= (plat->port_map ^ 0xf) << 24; in broadwell_sata_init()
76 reg32 |= (plat->devslp_mux & 1) << 15; in broadwell_sata_init()
79 /* Initialize AHCI memory-mapped space */ in broadwell_sata_init()
84 /* CAP (HBA Capabilities) : enable power management */ in broadwell_sata_init()
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/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dsata.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2008-2009 coresystems GmbH
27 /* Port enable */ in common_sata_init()
41 const void *blob = gd->fdt_blob; in bd82x6x_sata_init()
50 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); in bd82x6x_sata_init()
54 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); in bd82x6x_sata_init()
73 /* Initialize AHCI memory-mapped space */ in bd82x6x_sata_init()
76 /* CAP (HBA Capabilities) : enable power management */ in bd82x6x_sata_init()
90 /* CAP2 (HBA Capabilities Extended)*/ in bd82x6x_sata_init()
123 debug("SATA: Controller in plain-ide mode\n"); in bd82x6x_sata_init()
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/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
49 u32 cap; member
82 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) in ahci_port_base() argument
84 return base + 0x100 + (port * 0x80); in ahci_port_base()
99 return (i < timeout_msec) ? 0 : -1; in waiting_for_cmd_completed()
104 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_setup_oobr()
106 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); in ahci_setup_oobr()
107 writel(0x02060b14, &host_mmio->oobr); in ahci_setup_oobr()
117 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_host_init()
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/openbmc/qemu/tests/qtest/libqos/
H A Dahci.c29 #include "pci-pc.h"
31 #include "qemu/host-utils.h"
86 uint8_t port; member
107 g_assert(ahci->parent); in ahci_alloc()
108 return qmalloc(ahci->parent, bytes); in ahci_alloc()
114 g_assert(ahci->parent); in ahci_free()
115 qfree(ahci->parent, addr); in ahci_free()
118 bool is_atapi(AHCIQState *ahci, uint8_t port) in is_atapi() argument
120 return ahci_px_rreg(ahci, port, AHCI_PX_SIG) == AHCI_SIGNATURE_CDROM; in is_atapi()
156 QPCIBus *pcibus = dev ? dev->bus : NULL; in free_ahci_device()
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H A Dahci.h30 #include "malloc-pc.h"
44 /*** AHCI/HBA Register Offsets and Bitmasks ***/
106 /*** Port Memory Offsets & Bitmasks ***/
320 #define ATA_DEVICE_MAGIC 0xA0 /* used in ata1-3 */
342 uint32_t cap; member
344 AHCIPortQState port[32]; member
358 * Register device-to-host FIS structure.
380 * Register device-to-host FIS structure;
405 * Register host-to-device FIS structure.
428 * Register host-to-device FIS structure, for NCQ commands.
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/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
21 compatible = "rockchip,rk3588-i2s-tdm";
25 clock-names = "mclk_tx", "mclk_rx", "hclk";
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
29 dma-names = "tx";
30 power-domains = <&power RK3588_PD_VO0>;
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/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_bsg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
12 #include <linux/bsg-lib.h>
25 struct bsg_job *bsg_job = sp->u.bsg_job; in qla2x00_bsg_job_done()
26 struct fc_bsg_reply *bsg_reply = bsg_job->reply; in qla2x00_bsg_job_done()
27 struct completion *comp = sp->comp; in qla2x00_bsg_job_done()
29 ql_dbg(ql_dbg_user, sp->vha, 0x7009, in qla2x00_bsg_job_done()
31 __func__, sp->handle, res, bsg_job); in qla2x00_bsg_job_done()
34 kref_put(&sp->cmd_kref, qla2x00_sp_release); in qla2x00_bsg_job_done()
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H A Dqla_os.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
15 #include <linux/blk-mq-pci.h>
65 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
71 "beginning. Default is 0 - class 2 not supported.");
82 "Maximum number of command retries to a port that returns "
83 "a PORT-DOWN status.");
90 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
101 "during HBA initialization. Memory allocation requirements "
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/openbmc/linux/drivers/scsi/
H A Dhpsa.h3 * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
5 * Copyright 2014-2015 PMC-Sierra, Inc.
6 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
47 struct sas_port *port; member
74 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
75 unsigned char model[16]; /* bytes 16-31 of inquiry data */
113 int external; /* 1-from external array 0-not <0-unknown */
216 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
227 /* cap concurrent passthrus at some reasonable maximum */
256 /* Address of h->q[x] is passed to intr handler to know which queue */
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/openbmc/linux/arch/parisc/kernel/
H A Dhardware.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on the document "PA-RISC 1.1 I/O Firmware Architecture
73 {HPHW_NPROC,0x312,0x4,0x81,"Strider-50 (715S/50)"},
74 {HPHW_NPROC,0x313,0x4,0x81,"Strider-33 (715S/33)"},
75 {HPHW_NPROC,0x314,0x4,0x81,"Trailways-50 (715T/50)"},
76 {HPHW_NPROC,0x315,0x4,0x81,"Trailways-33 (715T/33)"},
87 {HPHW_NPROC,0x482,0x4,0x81,"WB-80 (E35)"},
88 {HPHW_NPROC,0x483,0x4,0x81,"WB-96 (E45)"},
89 {HPHW_NPROC,0x484,0x4,0x81,"UL Proc L-100 (811/D210,D310)"},
90 {HPHW_NPROC,0x485,0x4,0x81,"UL Proc L-75 (801/D200)"},
[all …]

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