30 #include "malloc-pc.h"
44 /*** AHCI/HBA Register Offsets and Bitmasks ***/
106 /*** Port Memory Offsets & Bitmasks ***/
320 #define ATA_DEVICE_MAGIC 0xA0 /* used in ata1-3 */
342     uint32_t cap;  member
344     AHCIPortQState port[32];  member
358  * Register device-to-host FIS structure.
380  * Register device-to-host FIS structure;
405  * Register host-to-device FIS structure.
428  * Register host-to-device FIS structure, for NCQ commands.
455  * The command list contains between 1-32 of these structures.
458     uint16_t flags; /* Cmd-Fis-Len, PMP#, and flags. */
472     uint32_t dbc;  /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
481     unsigned prd_size;  /* Size per-each PRD */
505 /* Helpers for reading/writing AHCI HBA register values */
509     return qpci_io_readl(ahci->dev, ahci->hba_bar, offset);  in ahci_mread()
514     qpci_io_writel(ahci->dev, ahci->hba_bar, offset, value);  in ahci_mwrite()
537 static inline size_t ahci_px_offset(uint8_t port, uint32_t reg_num)  in ahci_px_offset()  argument
539     return AHCI_PORTS + (HBA_PORT_NUM_REG * port) + reg_num;  in ahci_px_offset()
542 static inline uint32_t ahci_px_rreg(AHCIQState *ahci, uint8_t port,  in ahci_px_rreg()  argument
545     return ahci_rreg(ahci, ahci_px_offset(port, reg_num));  in ahci_px_rreg()
548 static inline void ahci_px_wreg(AHCIQState *ahci, uint8_t port,  in ahci_px_wreg()  argument
551     ahci_wreg(ahci, ahci_px_offset(port, reg_num), value);  in ahci_px_wreg()
554 static inline void ahci_px_set(AHCIQState *ahci, uint8_t port,  in ahci_px_set()  argument
557     ahci_px_wreg(ahci, port, reg_num,  in ahci_px_set()
558                  ahci_px_rreg(ahci, port, reg_num) | mask);  in ahci_px_set()
561 static inline void ahci_px_clr(AHCIQState *ahci, uint8_t port,  in ahci_px_clr()  argument
564     ahci_px_wreg(ahci, port, reg_num,  in ahci_px_clr()
565                  ahci_px_rreg(ahci, port, reg_num) & ~mask);  in ahci_px_clr()
580 /* Port Management */
582 void ahci_port_clear(AHCIQState *ahci, uint8_t port);
585 unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port);
586 void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
588 void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
590 void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot);
596 void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot);
601 bool is_atapi(AHCIQState *ahci, uint8_t port);
604 void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
606 AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
609 void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
611 void ahci_exec(AHCIQState *ahci, uint8_t port,
613 void ahci_atapi_test_ready(AHCIQState *ahci, uint8_t port, bool ready,
615 void ahci_atapi_get_sense(AHCIQState *ahci, uint8_t port,
617 void ahci_atapi_eject(AHCIQState *ahci, uint8_t port);
618 void ahci_atapi_load(AHCIQState *ahci, uint8_t port);
620 /* Command: Fine-grained lifecycle */
623 void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port);