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/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Daltera_pio.txt1 Altera GPIO controller bindings
4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
9 - altr,gpio-bank-width: Width of the GPIO bank. This defines how many pins the
10 GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
12 - gpio-bank-name: bank name attached to this device.
16 user_led_pio_8out: gpio@0x4cc0 {
17 compatible = "altr,pio-1.0";
20 altr,gpio-bank-width = <8>;
[all …]
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-networking/mctp/files/
H A Dsetup-static-endpoints3 # Setup Endpoint for NICs, using devmem to read GPIO value since
4 # the gpio pin is occupied by gpio-monitor, read the value from
7 # shellcheck source=meta-facebook/meta-yosemite4/recipes-networking/mctp/files/nic-gpio-addrs
8 . /usr/libexec/mctp/nic-gpio-addrs
11 gpio_val=$(devmem "$PRSNT_NIC0" "$WIDTH")
12 if [ $((gpio_val & "$BITMASK_NIC0")) -eq 0 ]; then
13 systemctl start setup-nic-endpoint-slot@0.service
17 gpio_val=$(devmem "$PRSNT_NIC1" "$WIDTH")
18 if [ $((gpio_val & "$BITMASK_NIC1")) -eq 0 ]; then
19 systemctl start setup-nic-endpoint-slot@1.service
[all …]
H A Dnic-gpio-addrs3 # shellcheck source=meta-facebook/meta-yosemite4/recipes-yosemite4/plat-tool/files/yosemite4-common…
4 . /usr/libexec/yosemite4-common-functions
8 if [ -n "$is_nuvoton_board" ]
10 WIDTH=32
11 # PRSNT_NIC0 is at the 23th bit (GPIO Bank5: GPIO183), 0 means NIC is present
15 # PRSNT_NIC1 is at the 29th bit (GPIO Bank5: GPIO189), 0 means NIC is present
19 # PRSNT_NIC2 is at the 28th bit (GPIO Bank2: GPIO92), 0 means NIC is present
23 # PRSNT_NIC3 is at the 24th bit (GPIO Bank5: GPIO184), 0 means NIC is present
27 WIDTH=8
/openbmc/u-boot/arch/nios2/dts/
H A D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,jr2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
H A Dmscc,serval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
H A Dmscc,servalt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3xmb_cmp.dtsi2 * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board
14 u-boot,dm-pre-reloc;
15 stdout-path = &dbgu;
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
26 bus-width = <4>;
27 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
35 compatible = "spi-flash";
36 spi-max-frequency = <50000000>;
42 atmel,clk-from-rk-pin;
[all …]
H A Dtegra210-p2371-0000.dts1 /dts-v1/;
6 model = "NVIDIA P2371-0000";
7 compatible = "nvidia,p2371-0000", "nvidia,tegra210";
10 stdout-path = &uarta;
26 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
27 power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
28 bus-width = <4>;
33 bus-width = <8>;
34 non-removable;
39 clock-frequency = <400000>;
[all …]
H A Dkeystone-k2l.dtsi13 #address-cells = <1>;
14 #size-cells = <0>;
16 interrupt-parent = <&gic>;
19 compatible = "arm,cortex-a15";
25 compatible = "arm,cortex-a15";
32 /include/ "keystone-k2l-clocks.dtsi"
36 current-speed = <115200>;
37 reg-shift = <2>;
38 reg-io-width = <4>;
46 current-speed = <115200>;
[all …]
H A Dsama5d3xmb.dtsi2 * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
15 u-boot,dm-pre-reloc;
16 stdout-path = &dbgu;
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
25 u-boot,dm-pre-reloc;
28 bus-width = <4>;
29 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
35 u-boot,dm-pre-reloc;
38 compatible = "spi-flash";
[all …]
H A Dtegra124-venice2.dts1 /dts-v1/;
10 stdout-path = &uarta;
35 clock-frequency = <100000>;
40 clock-frequency = <100000>;
45 clock-frequency = <100000>;
50 clock-frequency = <100000>;
55 clock-frequency = <400000>;
60 clock-frequency = <400000>;
65 spi-max-frequency = <25000000>;
70 spi-max-frequency = <25000000>;
[all …]
H A Dtegra114-dalmore.dts1 /dts-v1/;
10 stdout-path = &uartd;
32 clock-frequency = <100000>;
37 clock-frequency = <100000>;
42 clock-frequency = <100000>;
47 clock-frequency = <100000>;
52 clock-frequency = <400000>;
57 spi-max-frequency = <25000000>;
61 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
62 bus-width = <4>;
[all …]
H A Dast2600-greatlakes.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
9 compatible = "facebook,greatlakes-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
27 clock-frequency = <800000000>;
30 clock-frequency = <800000000>;
36 u-boot,dm-pre-reloc;
41 clock-frequency = <400000000>;
58 pinctrl-names = "default";
[all …]
H A Darmada-3720-uDPU.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
12 /dts-v1/;
14 #include "armada-37xx.dtsi"
15 #include "armada-3720-uDPU-u-boot.dtsi"
22 stdout-path = "serial0:115200n8";
38 #address-cells = <1>;
39 #size-cells = <0>;
40 ethphy0: ethernet-phy@0 {
43 ethphy1: ethernet-phy@1 {
[all …]
H A Dhi3798cv200-poplar.dts4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 * SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
14 #include "poplar-pinctrl.dtsi"
18 compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
26 stdout-path = "serial0:115200n8";
36 compatible = "linaro,optee-tz";
42 compatible = "gpio-leds";
44 user-led0 {
[all …]
H A Dat91sam9m10g45ek.dts2 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
9 /dts-v1/;
11 #include <dt-bindings/pwm/pwm.h>
14 model = "Atmel AT91SAM9M10G45-EK";
19 stdout-path = "serial0:115200n8";
20 u-boot,dm-pre-reloc;
29 clock-frequency = <32768>;
33 clock-frequency = <12000000>;
41 u-boot,dm-pre-reloc;
45 pinctrl-0 =
[all …]
H A Dtegra210-p2371-2180.dts1 /dts-v1/;
6 model = "NVIDIA P2371-2180";
7 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
10 stdout-path = &uarta;
24 pcie-controller@01003000 {
37 pinctrl-0 = <&padctl_default>;
38 pinctrl-names = "default";
42 nvidia,lanes = "otg-1", "otg-2";
48 nvidia,lanes = "pcie-5", "pcie-6";
53 pcie-x1 {
[all …]
H A Dtegra30-colibri.dts1 /dts-v1/;
10 stdout-path = &uarta;
36 clock-frequency = <400000>;
46 clock-frequency = <10000>;
55 clock-frequency = <100000>;
61 spi-max-frequency = <25000000>;
66 bus-width = <4>;
67 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
72 bus-width = <8>;
73 non-removable;
[all …]
H A Dr8a7794-alt.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
26 stdout-path = "serial0:115200n8";
34 d3_3v: regulator-d3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "D3.3V";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-boot-on;
[all …]
H A Dtegra20-trimslice.dts1 /dts-v1/;
10 stdout-path = &uarta;
25 clock-frequency = <216000000>;
30 spi-max-frequency = <25000000>;
33 pcie-controller@80003000 {
36 avdd-pex-supply = <&pci_vdd_reg>;
37 vdd-pex-supply = <&pci_vdd_reg>;
38 avdd-pex-pll-supply = <&pci_vdd_reg>;
39 avdd-plle-supply = <&pci_vdd_reg>;
40 vddio-pex-clk-supply = <&pci_clk_reg>;
[all …]
H A Dsun8i-h2-plus-bananapi-m2-zero.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Based on sun8i-h3-bananapi-m2-plus.dts, which is:
6 * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
9 /dts-v1/;
10 #include "sun8i-h3.dtsi"
11 #include "sunxi-common-regulators.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
17 model = "Banana Pi BPI-M2-Zero";
18 compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt5 compatible: should be "samsung,exynos-fimd"
9 samsung,vl-col: X resolution of the panel
10 samsung,vl-row: Y resolution of the panel
11 samsung,vl-freq: Refresh rate
12 samsung,vl-bpix: Bits per pixel
13 samsung,vl-hspw: Hsync value
14 samsung,vl-hfpd: Right margin
15 samsung,vl-hbpd: Left margin
16 samsung,vl-vspw: Vsync value
17 samsung,vl-vfpd: Lower margin
[all …]
/openbmc/u-boot/board/samsung/common/
H A Dboard.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <asm/gpio.h>
27 #include <dwc3-uboot.h>
80 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); in board_init()
82 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { in board_init()
84 return -1; in board_init()
92 gd->ram_size -= size; in board_init()
93 gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; in board_init()
105 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); in dram_init()
119 gd->bd->bi_dram[i].start = addr; in dram_init_banksize()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/nand/
H A Dnvidia,tegra20-nand.txt2 ----------
5 U-Boot. There should not be Linux-specific or U-Boot specific binding, just
12 - compatible : Should be "manufacturer,device", "nand-flash"
18 ----------------------
24 nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
26 nvidia,nand-width : bus width of the NAND device in bits
28 - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
33 non-EDO mode: Max(tRP, tREA) + 6ns
40 -------
42 nand-controller@0x70008000 {
[all …]

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