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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dxlnx,gpio-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI GPIO controller
10 - Neeli Srinivas <srinivas.neeli@amd.com>
13 The AXI GPIO design provides a general purpose input/output interface
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
22 - xlnx,xps-gpio-1.00.a
[all …]
H A Dgpio-mmio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic MMIO GPIO
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
[all …]
/openbmc/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
16 GPIO expander it is possible to use the driver with one of the popular I2C
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
29 - maxItems: 4
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx gpio driver for xps/axi_gpio IP.
5 * Copyright 2008 - 2013 Xilinx, Inc.
12 #include <linux/gpio/driver.h>
35 /* Read/Write access to the GPIO registers */
45 * struct xgpio_instance - Stores information about GPIO device
46 * @gc: GPIO chip
48 * @hw_map: GPIO pin mapping on hardware side
49 * @sw_map: GPIO pin mapping on software side
50 * @state: GPIO write state shadow register
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Daltera_pio.txt1 Altera GPIO controller bindings
4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
9 - altr,gpio-bank-width: Width of the GPIO bank. This defines how many pins the
10 GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
12 - gpio-bank-name: bank name attached to this device.
16 user_led_pio_8out: gpio@0x4cc0 {
17 compatible = "altr,pio-1.0";
20 altr,gpio-bank-width = <8>;
[all …]
/openbmc/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.h1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
18 #define MUX_PG(group_name, reg, shift, width) \ argument
27 .mfpctl_width = width, \
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
[all …]
H A Dpinctrl-owl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
14 #include <linux/gpio/driver.h>
25 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-owl.h"
35 * struct owl_pinctrl - pinctrl state of the device
38 * @chip: gpio chip
70 u32 bit, u32 width) in owl_read_field() argument
74 tmp = readl_relaxed(pctrl->base + reg); in owl_read_field()
[all …]
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-networking/mctp/files/
H A Dsetup-static-endpoints3 # Setup Endpoint for NICs, using devmem to read GPIO value since
4 # the gpio pin is occupied by gpio-monitor, read the value from
7 # shellcheck source=meta-facebook/meta-yosemite4/recipes-networking/mctp/files/nic-gpio-addrs
8 . /usr/libexec/mctp/nic-gpio-addrs
11 gpio_val=$(devmem "$PRSNT_NIC0" "$WIDTH")
12 if [ $((gpio_val & "$BITMASK_NIC0")) -eq 0 ]; then
13 systemctl start setup-nic-endpoint-slot@0.service
17 gpio_val=$(devmem "$PRSNT_NIC1" "$WIDTH")
18 if [ $((gpio_val & "$BITMASK_NIC1")) -eq 0 ]; then
19 systemctl start setup-nic-endpoint-slot@1.service
[all …]
/openbmc/linux/arch/arm/mach-s3c/
H A Dsetup-sdhci-gpio-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0
7 // S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
14 #include <linux/gpio.h>
16 #include "gpio-cfg.h"
18 #include "gpio-samsung.h"
20 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) in s3c64xx_setup_sdhci0_cfg_gpio() argument
22 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; in s3c64xx_setup_sdhci0_cfg_gpio()
24 /* Set all the necessary GPG pins to special-function 2 */ in s3c64xx_setup_sdhci0_cfg_gpio()
25 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); in s3c64xx_setup_sdhci0_cfg_gpio()
27 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { in s3c64xx_setup_sdhci0_cfg_gpio()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dgpio-control-nand.txt1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
15 GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
[all …]
H A Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
20 - enum:
21 - ti,am64-nand
22 - ti,omap2-nand
29 - description: Interrupt for fifoevent
[all …]
/openbmc/linux/tools/testing/selftests/gpio/
H A Dgpio-mockup.sh1 #!/bin/bash -efu
2 # SPDX-License-Identifier: GPL-2.0
7 #4: skip test - including run as non-root user
13 module="gpio-mockup"
29 echo "$0 [-frv] [-t type]"
30 echo "-f: full test (minimal set run by default)"
31 echo "-r: test random lines as well as fence posts"
32 echo "-t: interface type:"
33 echo " cdev (character device ABI) - default"
36 echo "-v: verbose progress reporting"
[all …]
/openbmc/u-boot/arch/nios2/dts/
H A D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
[all …]
/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dorion5x-rd88f5182-nas.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "orion5x-mv88f5182.dtsi"
11 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
20 stdout-path = &uart0;
30 gpio-leds {
31 compatible = "gpio-leds";
32 pinctrl-0 = <&pmx_debug_led>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/bitmain/
H A Dbm1880.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3701-0000.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "tegra234-p3701.dtsi"
8 compatible = "nvidia,p3701-0000", "nvidia,tegra234";
19 vcc-supply = <&vdd_1v8_hs>;
20 address-width = <8>;
23 read-only;
31 compatible = "jedec,spi-nor";
33 spi-max-frequency = <102000000>;
34 spi-tx-bus-width = <4>;
35 spi-rx-bus-width = <4>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,jr2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
24 width-mm:
26 Specifies the width of the physical area where images are displayed. This
29 height-mm:
43 non-descriptive information. For instance an LCD panel in a system that
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3xmb_cmp.dtsi2 * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board
14 u-boot,dm-pre-reloc;
15 stdout-path = &dbgu;
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
26 bus-width = <4>;
27 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
35 compatible = "spi-flash";
36 spi-max-frequency = <50000000>;
42 atmel,clk-from-rk-pin;
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3xmb.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
21 bus-width = <4>;
22 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
31 spi-max-frequency = <50000000>;
37 atmel,clk-from-rk-pin;
50 clock-names = "mclk";
58 pinctrl-names = "default";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt5 compatible: should be "samsung,exynos-fimd"
9 samsung,vl-col: X resolution of the panel
10 samsung,vl-row: Y resolution of the panel
11 samsung,vl-freq: Refresh rate
12 samsung,vl-bpix: Bits per pixel
13 samsung,vl-hspw: Hsync value
14 samsung,vl-hfpd: Right margin
15 samsung,vl-hbpd: Left margin
16 samsung,vl-vspw: Vsync value
17 samsung,vl-vfpd: Lower margin
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Dcu1000-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,sysost.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1000-neo", "ingenic,x1000e";
11 model = "YSH & ATIL General Board CU1000-Neo";
18 stdout-path = "serial2:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]
H A Dcu1830-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,sysost.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1830-neo", "ingenic,x1830";
11 model = "YSH & ATIL General Board CU1830-Neo";
18 stdout-path = "serial1:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]

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