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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dintel-gma.txt1 Intel GMA Bindings
9 - compatible : "intel,gma";
29 gma {
30 compatible = "intel,gma";
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dgtt.h85 unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma);
86 unsigned long (*gma_to_pte_index)(unsigned long gma);
87 unsigned long (*gma_to_pde_index)(unsigned long gma);
88 unsigned long (*gma_to_l3_pdp_index)(unsigned long gma);
89 unsigned long (*gma_to_l4_pdp_index)(unsigned long gma);
90 unsigned long (*gma_to_pml4_index)(unsigned long gma);
277 unsigned long gma);
H A Dcmd_parser.c1096 unsigned long gma; in cmd_handler_lrm() local
1109 gma = cmd_gma(s, i + 1); in cmd_handler_lrm()
1111 gma |= (cmd_gma_hi(s, i + 2)) << 32; in cmd_handler_lrm()
1112 ret |= cmd_address_audit(s, gma, sizeof(u32), false); in cmd_handler_lrm()
1124 unsigned long gma; in cmd_handler_srm() local
1133 gma = cmd_gma(s, i + 1); in cmd_handler_srm()
1135 gma |= (cmd_gma_hi(s, i + 2)) << 32; in cmd_handler_srm()
1136 ret |= cmd_address_audit(s, gma, sizeof(u32), false); in cmd_handler_srm()
1182 unsigned long gma; in cmd_handler_pipe_control() local
1202 gma = cmd_val(s, 2) & GENMASK(31, 3); in cmd_handler_pipe_control()
[all …]
H A Dtrace.h98 TP_PROTO(const char *prefix, unsigned long gma,
101 TP_ARGS(prefix, gma, index),
109 "%s gma 0x%lx index 0x%lx\n", prefix, gma, index);
117 unsigned long gma, unsigned long gpa),
119 TP_ARGS(id, type, ring_id, root_entry_type, gma, gpa),
127 "VM%d %s ring %d root_entry_type %d gma 0x%lx -> gpa 0x%lx\n",
128 id, type, ring_id, root_entry_type, gma, gpa);
H A Dgtt.c475 * Per-platform GMA routines.
477 static unsigned long gma_to_ggtt_pte_index(unsigned long gma) in gma_to_ggtt_pte_index() argument
479 unsigned long x = (gma >> I915_GTT_PAGE_SHIFT); in gma_to_ggtt_pte_index()
481 trace_gma_index(__func__, gma, x); in gma_to_ggtt_pte_index()
486 static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
489 trace_gma_index(__func__, gma, x); \
493 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
494 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
495 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
496 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
[all …]
H A Dfb_decoder.c254 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_primary_plane()
377 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_cursor_plane()
481 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_sprite_plane()
H A Dscheduler.c221 /* find consecutive GPAs from gma until the first inconsecutive GPA. in populate_shadow_context()
546 * here, rather than switch to shadow bb's gma in prepare_shadow_batch_buffer()
548 * gma address, and send original bb to hardware in prepare_shadow_batch_buffer()
983 /* find consecutive GPAs from gma until the first inconsecutive GPA. in update_guest_context()
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_drv.c48 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
49 * PowerVR SGX535 - Moorestown - Intel GMA 600
50 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
51 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
52 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.yaml36 dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma,
103 nvidia,pins = "atb", "gma", "gme";
/openbmc/openbmc/poky/meta/recipes-graphics/libva/
H A Dlibva.inc7 specification was originally designed by Intel for its GMA (Graphics \
/openbmc/linux/net/ncsi/
H A Dinternal.h89 #define NCSI_OEM_MLX_CMD_GMA_PARAM 0x1b /* Parameter for GMA */
325 unsigned int gma_flag; /* OEM GMA flag */
326 struct sockaddr pending_mac; /* MAC address received from GMA */
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-trimslice.dts49 nvidia,pins = "atb", "gma";
212 "gma", "gmc", "gmd", "gpu", "gpu7",
H A Dtegra20-tamonten.dtsi43 nvidia,pins = "atb", "gma", "gme";
187 "gma", "gmb", "gmc", "gmd", "gme", "gpu7",
H A Dtegra20-paz00.dts65 nvidia,pins = "atb", "gma", "gme";
203 "gma", "gmb", "gmc", "gmd", "gme",
H A Dtegra20-ventana.dts59 nvidia,pins = "atb", "gma", "gme";
210 "dap4", "ddc", "dtf", "gma", "gmc",
H A Dtegra20-harmony.dts57 nvidia,pins = "atb", "gma", "gme";
204 "cdev1", "cdev2", "dap1", "dtb", "gma",
H A Dtegra20-seaboard.dts57 nvidia,pins = "atb", "gma", "gme";
208 "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20-tamonten.dtsi32 nvidia,pins = "atb", "gma", "gme";
175 "cdev1", "cdev2", "dap1", "dtb", "gma",
H A Dtegra20-paz00.dts81 nvidia,pins = "atb", "gma", "gme";
219 "gma", "gmb", "gmc", "gmd", "gme",
H A Dtegra20-ventana.dts78 nvidia,pins = "atb", "gma", "gme";
229 "dap4", "ddc", "dtf", "gma", "gmc",
H A Dtegra20-harmony.dts78 nvidia,pins = "atb", "gma", "gme";
225 "cdev1", "cdev2", "dap1", "dtb", "gma",
/openbmc/u-boot/arch/x86/dts/
H A Dchromebook_link.dts352 gma@2,0 {
354 compatible = "intel,gma";
/openbmc/u-boot/arch/x86/include/asm/
H A Dcpu.h50 * UCLASS_VIDEO for the GMA device).
/openbmc/linux/Documentation/gpu/
H A Dkms-properties.csv40 CDV gma-500,Generic,"""Broadcast RGB""",ENUM,"{ “Full”, “Limited 16:235” }",Connector,TBD
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dpinmux.c316 PIN(GMA, UARTE, SPI3, GMI, SDIO4),

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