| /openbmc/linux/Documentation/virt/kvm/ |
| H A D | halt-polling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 The KVM halt polling system
7 The KVM halt polling system provides a feature within KVM whereby the latency
16 the order of a few micro-seconds, although performance benefits are workload
19 invoked. Thus halt polling is especially useful on workloads with very short
20 wakeup periods where the time spent halt polling is minimised and the time
23 The generic halt polling code is implemented in:
27 The powerpc kvm-hv specific case is implemented in:
31 Halt Polling Interval
35 as the halt polling interval, is increased and decreased based on the perceived
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| /openbmc/linux/Documentation/devicetree/bindings/input/ |
| H A D | azoteq,iqs7222.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
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| H A D | iqs269a.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
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| /openbmc/linux/arch/alpha/kernel/ |
| H A D | head.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * switched into OSF/1 PAL-code, and loaded us at the correct address
8 * the kernel global pointer and jump to the kernel entry-point.
12 #include <asm/asm-offsets.h>
29 lda $30,0x4000 - SIZEOF_PT_REGS($8)
39 /* On entry here from SRM console, the HWPCB of the per-cpu
88 # It is handy, on occasion, to make halt actually just loop.
94 .globl halt
95 .ent halt
96 halt: label
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | qcom,ssc-block-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
10 - Michael Srba <Michael.Srba@seznam.cz>
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
32 - description: SSCAON_CONFIG0 registers
33 - description: SSCAON_CONFIG1 registers
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| /openbmc/linux/Documentation/virt/ |
| H A D | guest-halt-polling.rst | 2 Guest halt polling
15 2) The VM-exit cost can be avoided.
20 The basic logic as follows: A global value, guest_halt_poll_ns,
25 ("per-cpu guest_halt_poll_ns"), which is adjusted by the algorithm
42 Division factor used to shrink per-cpu guest_halt_poll_ns when
43 wakeup event occurs after the global guest_halt_poll_ns.
49 Multiplication factor used to grow per-cpu guest_halt_poll_ns
50 when event occurs after per-cpu guest_halt_poll_ns
51 but before global guest_halt_poll_ns.
57 The per-cpu guest_halt_poll_ns eventually reaches zero
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| /openbmc/linux/arch/arm/mach-rockchip/ |
| H A D | sleep.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
24 /* olny cpu0 can continue to run, the others is halt here */
44 .global rkpm_bootdata_l2ctlr_f
49 .global rkpm_bootdata_l2ctlr
64 .word . - rockchip_slp_cpu_resume
|
| /openbmc/linux/arch/powerpc/platforms/cell/spufs/ |
| H A D | spu_restore_crt0.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * crt0_r.S: Entry function for SPU-side context restore.
7 * Entry and exit function for SPU-side of the context restore
22 .global _start
25 * (16kb-16). The back chain pointer is initialized
36 stqd $SP, -160($SP)
37 ai $SP, $SP, -160
42 .global exit
43 .global _exit
53 restore_reg_insts: /* must be quad-word aligned. */
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| /openbmc/linux/arch/arc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
108 ISA for the Next Generation ARC-HS cores
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
128 -Caches: New Prog Model, Region Flush
129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
132 bool "ARC-HS"
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| /openbmc/u-boot/drivers/dma/ |
| H A D | bcm6348-iudma.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Derived from linux/drivers/dma/bcm63xx-iudma.c:
12 * Copyright (C) 2000-2010 Broadcom Corporation
21 #include <dma-uclass.h>
35 /* DMA Global Configuration register */
43 /* DMA Global Flow Control registers */
50 /* DMA Global Reset register */
155 uint32_t cfg, halt; in bcm6348_iudma_chan_stop() local
158 halt = DMAC_CFG_PKT_HALT_MASK; in bcm6348_iudma_chan_stop()
160 halt = DMAC_CFG_BRST_HALT_MASK; in bcm6348_iudma_chan_stop()
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| /openbmc/linux/arch/mips/include/asm/mach-cavium-octeon/ |
| H A D | kernel-entry-init.h | 6 * Copyright (C) 2005-2008 Cavium Networks, Inc
48 xor t1, t1, 0x9000 # 63-P1
51 xor t1, t1, 0x9008 # 63-P2
54 xor t1, t1, 0x9100 # 68-P1
57 xor t1, t1, 0x9200 # 66-PX
60 slti t1, t1, 2 # 66-P1.2 and later good.
63 4: # core-16057 work around
66 5: # No core-16057 work around
77 sd $0, -32768(v0)
121 # Get my GP from the global variable
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | fsl_soc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
37 static phys_addr_t immrbase = -1;
43 if (immrbase != -1) in get_immrbase()
63 static u32 sysfreq = -1; in fsl_get_sys_freq()
66 if (sysfreq != -1) in fsl_get_sys_freq()
71 return -1; in fsl_get_sys_freq()
73 of_property_read_u32(soc, "clock-frequency", &sysfreq); in fsl_get_sys_freq()
74 if (sysfreq == -1 || !sysfreq) in fsl_get_sys_freq()
75 of_property_read_u32(soc, "bus-frequency", &sysfreq); in fsl_get_sys_freq()
86 static u32 brgfreq = -1; in get_brgfreq()
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| /openbmc/u-boot/doc/ |
| H A D | README.drivers.eth | 5 U-Boot core driver model. See doc/driver-model/README.txt
7 -----------------------
9 -----------------------
11 The networking stack in Das U-Boot is designed for multiple network devices
16 ------------------
18 ------------------
21 meaning of 0 for success and non-zero for failure.
23 ----------
25 ----------
27 When U-Boot initializes, it will call the common function eth_initialize().
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| /openbmc/u-boot/arch/mips/cpu/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for MIPS32 CPU-core
8 #include <asm-offsets.h>
55 li t0, -16
78 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
83 /* U-Boot entry point */
89 * Store some board-specific boot configuration. This is used by some
100 * cannot be handled. Halt execution and transfer control to debugger,
219 /* Set up initial stack and global data */
252 /* Set up initial stack and global data */
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| /openbmc/linux/tools/testing/selftests/kvm/x86_64/ |
| H A D | xapic_ipi_test.c | 1 // SPDX-License-Identifier: GPL-2.0
19 * Migration is a command line option. When used on non-numa machines will
20 * exit with error. Test is still usefull on non-numa for testing IPIs.
69 * Record local version register as a cross-check that APIC access
80 uint64_t *pipis_rcvd; /* host address of ipis_rcvd global */
96 data->halter_apic_id = GET_APIC_ID_FIELD(xapic_read_reg(APIC_ID)); in halter_guest_code()
97 data->halter_lvr = xapic_read_reg(APIC_LVR); in halter_guest_code()
102 * halt to the sender vCPU and executing the halt. No need to disable on in halter_guest_code()
104 * signal going into first halt before starting the sender vCPU. Record in halter_guest_code()
108 data->halter_tpr = xapic_read_reg(APIC_TASKPRI); in halter_guest_code()
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| /openbmc/linux/include/linux/fsl/ |
| H A D | guts.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Freecale 85xx and 86xx Global Utilties register set
18 * Global Utility Registers.
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
31 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
37 u8 res018[0x20 - 0x18];
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| /openbmc/linux/arch/mips/kernel/ |
| H A D | cps-vec.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <asm/asm-offsets.h>
16 #include <asm/smp-cps.h>
50 * Set dest to non-zero if the core supports the MT ASE, else zero. If
65 * Set dest to non-zero if the core supports MIPSr6 multithreading
96 .global mips_cps_core_entry_patch_end
159 /* Skip core-level init if we started up coherent */
163 /* Perform any further required core-level initialisation */
268 /* Set exclusive TC, non-active, master */
274 /* Set TC non-active, non-allocatable */
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| /openbmc/u-boot/board/synopsys/hsdk/ |
| H A D | hsdk.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 #include "clk-lib.h"
19 #include "env-lib.h"
23 #define ALL_CPU_MASK GENMASK(NR_CPUS - 1, 0)
29 #define BOOTSTAGE_2 2 /* after HW init, before self halt */
30 #define BOOTSTAGE_3 3 /* after self halt */
81 * Uncached cross-cpu structure. All CPUs must access to this structure fields
93 /* slave CPU status - bootstage number */
97 * Slave CPU data - it is copy of corresponding fields in
227 /* I$ is enabled - we need to disable it */ in init_master_icache()
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| /openbmc/qemu/docs/devel/ |
| H A D | multi-thread-tcg.rst | 2 Copyright (c) 2015-2020 Linaro Ltd.
5 later. See the COPYING file in the top-level directory.
8 Multi-threaded TCG
11 This document outlines the design for multi-threaded TCG (a.k.a MTTCG)
12 system-mode emulation. user-mode emulation has always mirrored the
15 linux-user emulation.
17 The original system-mode TCG implementation was single threaded and
18 dealt with multiple CPUs with simple round-robin scheduling. This
20 being emulated gained additional cores and per-core performance gains
27 user-space thread. This is enabled by default for all FE/BE
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| /openbmc/linux/arch/arc/kernel/ |
| H A D | entry-arcv2.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
58 .rept NR_CPU_IRQS - 8
65 flag 1 ; Unexpected event, halt
74 # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
81 # Note this disable is only for consistent book-keeping as further interrupts
84 # unless this one returns (or higher prio becomes pending in 2-prio scheme)
118 ; ---------------------------------------------
120 ; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
122 ; ---------------------------------------------
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| /openbmc/phosphor-state-manager/ |
| H A D | obmcutil | 1 #!/bin/bash -e
3 set -euo pipefail
9 USAGE="Usage: obmcutil [-h] [--wait] [--verbose] [--id=<INSTANCE_ID>]
20 HOST_TIMEOUT_TARGET=obmc-host-timeout@0.target
21 HOST_CRASH_TARGET=obmc-host-crash@0.target
23 ## NOTE: The following global variables are used only in the run_timeout cmd.
73 echo "obmcutil listlogs List all phosphor-logging entries on the"
79 echo "obmcutil deletelogs Delete all phosphor-logging entries from"
85 echo " -h, --help show this help message and exit"
86 echo " -w, --wait block until state transition succeeds or fails"
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| /openbmc/linux/arch/um/drivers/ |
| H A D | mconsole_user.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
17 * With uts namespaces, uts information becomes process-specific, so
23 { "halt", mconsole_halt, MCONSOLE_PROC },
48 msg.msg_name = &(req->origin); in mconsole_reply_v0()
49 msg.msg_namelen = req->originlen; in mconsole_reply_v0()
56 return sendmsg(req->originating_fd, &msg, 0); in mconsole_reply_v0()
66 if (!strncmp(req->request.data, cmd->command, in mconsole_parse()
67 strlen(cmd->command))) { in mconsole_parse()
83 req->originlen = sizeof(req->origin); in mconsole_get_request()
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| /openbmc/qemu/hw/ide/ |
| H A D | ahci-internal.h | 29 #include "ide-internal.h"
58 /* global controller registers */
61 AHCI_HOST_REG_CTL = 1, /* GHC: global host control */
75 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
76 #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
83 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
85 #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */
146 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
187 /* ap->flags bits */
305 bool halt; member
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| /openbmc/linux/drivers/infiniband/hw/hfi1/ |
| H A D | pio.c | 1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
3 * Copyright(c) 2015-2018 Intel Corporation.
32 /* global control of PIO send */
38 int flush = 0; /* re-read sendctrl to make sure it is flushed */ in pio_send_control()
41 spin_lock_irqsave(&dd->sendctrl_lock, flags); in pio_send_control()
50 for (i = 0; i < ARRAY_SIZE(dd->vld); i++) in pio_send_control()
51 if (!dd->vld[i].mtu) in pio_send_control()
86 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in pio_send_control()
93 #define SCS_POOL_0 -1
94 #define SCS_POOL_1 -2
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| /openbmc/u-boot/include/ |
| H A D | fsl_fman.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
24 u32 fmbm_gde; /* global debug enable */
41 u32 fmqm_gs; /* global status register */
119 /* FMBM_RCFG - Rx configuration */
124 /* FMBM_RST - Rx status */
127 /* FMBM_RFCA - Rx frame command attributes */
132 /* FMBM_RSTC - Rx statistics */
168 /* FMBM_TCFG - Tx configuration */
172 /* FMBM_TST - Tx status */
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