10b9fe9b7SMichael Srba# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 20b9fe9b7SMichael Srba%YAML 1.2 30b9fe9b7SMichael Srba--- 40b9fe9b7SMichael Srba$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# 50b9fe9b7SMichael Srba$schema: http://devicetree.org/meta-schemas/core.yaml# 60b9fe9b7SMichael Srba 70b9fe9b7SMichael Srbatitle: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs 80b9fe9b7SMichael Srba 90b9fe9b7SMichael Srbamaintainers: 100b9fe9b7SMichael Srba - Michael Srba <Michael.Srba@seznam.cz> 110b9fe9b7SMichael Srba 120b9fe9b7SMichael Srbadescription: | 130b9fe9b7SMichael Srba This binding describes the dependencies (clocks, resets, power domains) which 140b9fe9b7SMichael Srba need to be turned on in a sequence before communication over the AHB bus 150b9fe9b7SMichael Srba becomes possible. 160b9fe9b7SMichael Srba 170b9fe9b7SMichael Srba Additionally, the reg property is used to pass to the driver the location of 180b9fe9b7SMichael Srba two sadly undocumented registers which need to be poked as part of the sequence. 190b9fe9b7SMichael Srba 200b9fe9b7SMichael Srba The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart 210b9fe9b7SMichael Srba controllers, a hexagon core, and a clock controller which provides clocks for 220b9fe9b7SMichael Srba the above. 230b9fe9b7SMichael Srba 240b9fe9b7SMichael Srbaproperties: 250b9fe9b7SMichael Srba compatible: 260b9fe9b7SMichael Srba items: 270b9fe9b7SMichael Srba - const: qcom,msm8998-ssc-block-bus 280b9fe9b7SMichael Srba - const: qcom,ssc-block-bus 290b9fe9b7SMichael Srba 300b9fe9b7SMichael Srba reg: 31*2aa0d4c8SKrzysztof Kozlowski items: 32*2aa0d4c8SKrzysztof Kozlowski - description: SSCAON_CONFIG0 registers 33*2aa0d4c8SKrzysztof Kozlowski - description: SSCAON_CONFIG1 registers 340b9fe9b7SMichael Srba 350b9fe9b7SMichael Srba reg-names: 360b9fe9b7SMichael Srba items: 370b9fe9b7SMichael Srba - const: mpm_sscaon_config0 380b9fe9b7SMichael Srba - const: mpm_sscaon_config1 390b9fe9b7SMichael Srba 400b9fe9b7SMichael Srba '#address-cells': 410b9fe9b7SMichael Srba enum: [ 1, 2 ] 420b9fe9b7SMichael Srba 430b9fe9b7SMichael Srba '#size-cells': 440b9fe9b7SMichael Srba enum: [ 1, 2 ] 450b9fe9b7SMichael Srba 460b9fe9b7SMichael Srba ranges: true 470b9fe9b7SMichael Srba 480b9fe9b7SMichael Srba clocks: 490b9fe9b7SMichael Srba maxItems: 6 500b9fe9b7SMichael Srba 510b9fe9b7SMichael Srba clock-names: 520b9fe9b7SMichael Srba items: 530b9fe9b7SMichael Srba - const: xo 540b9fe9b7SMichael Srba - const: aggre2 550b9fe9b7SMichael Srba - const: gcc_im_sleep 560b9fe9b7SMichael Srba - const: aggre2_north 570b9fe9b7SMichael Srba - const: ssc_xo 580b9fe9b7SMichael Srba - const: ssc_ahbs 590b9fe9b7SMichael Srba 600b9fe9b7SMichael Srba power-domains: 61*2aa0d4c8SKrzysztof Kozlowski items: 62*2aa0d4c8SKrzysztof Kozlowski - description: CX power domain 63*2aa0d4c8SKrzysztof Kozlowski - description: MX power domain 640b9fe9b7SMichael Srba 650b9fe9b7SMichael Srba power-domain-names: 660b9fe9b7SMichael Srba items: 670b9fe9b7SMichael Srba - const: ssc_cx 680b9fe9b7SMichael Srba - const: ssc_mx 690b9fe9b7SMichael Srba 700b9fe9b7SMichael Srba resets: 71*2aa0d4c8SKrzysztof Kozlowski items: 72*2aa0d4c8SKrzysztof Kozlowski - description: Main reset 73*2aa0d4c8SKrzysztof Kozlowski - description: 74*2aa0d4c8SKrzysztof Kozlowski SSC Branch Control Register reset (associated with the ssc_xo and 75*2aa0d4c8SKrzysztof Kozlowski ssc_ahbs clocks) 760b9fe9b7SMichael Srba 770b9fe9b7SMichael Srba reset-names: 780b9fe9b7SMichael Srba items: 790b9fe9b7SMichael Srba - const: ssc_reset 800b9fe9b7SMichael Srba - const: ssc_bcr 810b9fe9b7SMichael Srba 820b9fe9b7SMichael Srba qcom,halt-regs: 830b9fe9b7SMichael Srba $ref: /schemas/types.yaml#/definitions/phandle-array 840b9fe9b7SMichael Srba description: describes how to locate the ssc AXI halt register 850b9fe9b7SMichael Srba items: 860b9fe9b7SMichael Srba - items: 870b9fe9b7SMichael Srba - description: Phandle reference to a syscon representing TCSR 880b9fe9b7SMichael Srba - description: offset for the ssc AXI halt register 890b9fe9b7SMichael Srba 900b9fe9b7SMichael Srbarequired: 910b9fe9b7SMichael Srba - compatible 920b9fe9b7SMichael Srba - reg 930b9fe9b7SMichael Srba - reg-names 940b9fe9b7SMichael Srba - '#address-cells' 950b9fe9b7SMichael Srba - '#size-cells' 960b9fe9b7SMichael Srba - ranges 970b9fe9b7SMichael Srba - clocks 980b9fe9b7SMichael Srba - clock-names 990b9fe9b7SMichael Srba - power-domains 1000b9fe9b7SMichael Srba - power-domain-names 1010b9fe9b7SMichael Srba - resets 1020b9fe9b7SMichael Srba - reset-names 1030b9fe9b7SMichael Srba - qcom,halt-regs 1040b9fe9b7SMichael Srba 1050b9fe9b7SMichael SrbaadditionalProperties: 1060b9fe9b7SMichael Srba type: object 1070b9fe9b7SMichael Srba 1080b9fe9b7SMichael Srbaexamples: 1090b9fe9b7SMichael Srba - | 1100b9fe9b7SMichael Srba #include <dt-bindings/clock/qcom,gcc-msm8998.h> 1110b9fe9b7SMichael Srba #include <dt-bindings/clock/qcom,rpmcc.h> 1120b9fe9b7SMichael Srba #include <dt-bindings/power/qcom-rpmpd.h> 1130b9fe9b7SMichael Srba 1140b9fe9b7SMichael Srba soc { 1150b9fe9b7SMichael Srba #address-cells = <1>; 1160b9fe9b7SMichael Srba #size-cells = <1>; 1170b9fe9b7SMichael Srba 1180b9fe9b7SMichael Srba // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; 1190b9fe9b7SMichael Srba ssc_ahb_slave: bus@10ac008 { 1200b9fe9b7SMichael Srba #address-cells = <1>; 1210b9fe9b7SMichael Srba #size-cells = <1>; 1220b9fe9b7SMichael Srba ranges; 1230b9fe9b7SMichael Srba 1240b9fe9b7SMichael Srba compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus"; 1250b9fe9b7SMichael Srba reg = <0x10ac008 0x4>, <0x10ac010 0x4>; 1260b9fe9b7SMichael Srba reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; 1270b9fe9b7SMichael Srba 1280b9fe9b7SMichael Srba clocks = <&xo>, 1290b9fe9b7SMichael Srba <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 1300b9fe9b7SMichael Srba <&gcc GCC_IM_SLEEP>, 1310b9fe9b7SMichael Srba <&gcc AGGRE2_SNOC_NORTH_AXI>, 1320b9fe9b7SMichael Srba <&gcc SSC_XO>, 1330b9fe9b7SMichael Srba <&gcc SSC_CNOC_AHBS_CLK>; 1340b9fe9b7SMichael Srba clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; 1350b9fe9b7SMichael Srba 1360b9fe9b7SMichael Srba resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; 1370b9fe9b7SMichael Srba reset-names = "ssc_reset", "ssc_bcr"; 1380b9fe9b7SMichael Srba 1390b9fe9b7SMichael Srba power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; 1400b9fe9b7SMichael Srba power-domain-names = "ssc_cx", "ssc_mx"; 1410b9fe9b7SMichael Srba 1420b9fe9b7SMichael Srba qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; 1430b9fe9b7SMichael Srba }; 1440b9fe9b7SMichael Srba }; 145