/openbmc/linux/Documentation/devicetree/bindings/ata/ |
H A D | ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Common Properties for Serial ATA AHCI controllers 10 - Hans de Goede <hdegoede@redhat.com> 11 - Damien Le Moal <dlemoal@kernel.org> 14 This document defines device tree properties for a common AHCI SATA 18 document doesn't constitute a DT-node binding by itself but merely 19 defines a set of common properties for the AHCI-compatible devices. [all …]
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H A D | ahci-platform.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: AHCI SATA Controller 10 SATA nodes are defined to describe on-chip Serial ATA controllers. 13 It is possible, but not required, to represent each port as a sub-node. 18 - Hans de Goede <hdegoede@redhat.com> 19 - Jens Axboe <axboe@kernel.dk> 26 - brcm,iproc-ahci [all …]
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H A D | qcom-sata.txt | 1 * Qualcomm AHCI SATA Controller 3 SATA nodes are defined to describe on-chip Serial ATA controllers. 7 - compatible : compatible list, must contain "generic-ahci" 8 - interrupts : <interrupt mapping for SATA IRQ> 9 - reg : <registers mapping> 10 - phys : Must contain exactly one entry as specified 11 in phy-bindings.txt 12 - phy-names : Must be "sata-phy" 14 Required properties for "qcom,ipq806x-ahci" compatible: 15 - clocks : Must contain an entry for each entry in clock-names. [all …]
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H A D | snps,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Synopsys DWC AHCI SATA controller 10 - Serge Semin <fancer.lancer@gmail.com> 13 This document defines device tree bindings for the generic Synopsys DWC 14 implementation of the AHCI SATA controller. 20 - snps,dwc-ahci 21 - snps,spear-ahci [all …]
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H A D | snps,dwc-ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Synopsys DWC AHCI SATA controller properties 10 - Serge Semin <fancer.lancer@gmail.com> 13 This document defines device tree schema for the generic Synopsys DWC 14 AHCI controller properties. 19 - $ref: ahci-common.yaml# 30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock, [all …]
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/openbmc/linux/drivers/ata/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 10 uses pata-platform driver to enable the relevant driver in the 21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or 62 <file:Documentation/admin-guide/kernel-parameters.txt>. 76 This option adds support for ATA-related ACPI objects. 107 comment "Controllers with non-SFF native interface" 110 tristate "AHCI SATA support" 114 This option enables support for AHCI Serial ATA. 125 for chipsets / "South Bridges" supporting low-power modes. Such 140 tristate "Platform AHCI SATA support" [all …]
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H A D | ahci_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * AHCI SATA platform driver 5 * Copyright 2004-2005 Red Hat, Inc. 21 #include "ahci.h" 23 #define DRV_NAME "ahci" 45 struct device *dev = &pdev->dev; in ahci_probe() 59 if (device_is_compatible(dev, "hisilicon,hisi-ahci")) in ahci_probe() 60 hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; in ahci_probe() 81 { .compatible = "generic-ahci", }, 83 { .compatible = "ibm,476gtr-ahci", }, [all …]
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H A D | ahci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * ahci.c - AHCI SATA support 6 * Please ALWAYS copy linux-ide@vger.kernel.org 9 * Copyright 2004-2005 Red Hat, Inc. 12 * as Documentation/driver-api/libata.rst 14 * AHCI hardware documentation: 25 #include <linux/dma-mapping.h> 32 #include <linux/ahci-remap.h> 33 #include <linux/io-64-nonatomic-lo-hi.h> 34 #include "ahci.h" [all …]
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/4xx/ |
H A D | akebono.txt | 11 - model : "ibm,akebono". 12 - compatible : "ibm,akebono" , "ibm,476gtr". 20 - compatible : should be "ibm,476gtr-sdhci","generic-sdhci". 21 - reg : should contain the SDHCI registers location and length. 22 - interrupts : should contain the SDHCI interrupt. 24 1.b) The Advanced Host Controller Interface (AHCI) SATA node 30 - compatible : should be "ibm,476gtr-ahci". 31 - reg : should contain the AHCI registers location and length. 32 - interrupts : should contain the AHCI interrupt. 41 - compatible : should be "ibm,akebono-fpga". [all …]
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/openbmc/u-boot/doc/ |
H A D | README.qemu-arm | 1 # SPDX-License-Identifier: GPL-2.0+ 5 U-Boot on QEMU's 'virt' machine on ARM & AArch64 9 virtualization purposes. This document describes how to run U-Boot under it. 10 Both 32-bit ARM and AArch64 are supported. 14 - A freely configurable amount of CPU cores 15 - U-Boot loaded and executing in the emulated flash at address 0x0 16 - A generated device tree blob placed at the start of RAM 17 - A freely configurable amount of RAM, described by the DTB 18 - A PL011 serial port, discoverable via the DTB 19 - An ARMv7/ARMv8 architected timer [all …]
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/openbmc/qemu/docs/system/arm/ |
H A D | sbsa.rst | 1 Arm Server Base System Architecture Reference board (``sbsa-ref``) 4 The ``sbsa-ref`` board intends to look like real hardware (while the ``virt`` 5 board is a generic board platform that doesn't match any real hardware). 9 - `Base System Architecture <https://developer.arm.com/documentation/den0094/>`__ (BSA) 10 - `Server Base System Architecture <https://developer.arm.com/documentation/den0029/>`__ (SBSA) 21 The ``sbsa-ref`` board supports: 23 - A configurable number of AArch64 CPUs 24 - GIC version 3 25 - System bus AHCI controller 26 - System bus XHCI controller [all …]
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/openbmc/linux/arch/arm/boot/dts/socionext/ |
H A D | uniphier-pro4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 compatible = "socionext,uniphier-pro4"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 22 compatible = "arm,cortex-a9"; [all …]
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H A D | uniphier-pxs2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/thermal/thermal.h> 13 compatible = "socionext,uniphier-pxs2"; 14 #address-cells = <1>; 15 #size-cells = <1>; 18 #address-cells = <1>; 19 #size-cells = <0>; [all …]
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/openbmc/qemu/tests/qtest/libqos/ |
H A D | ahci.h | 5 * AHCI qtest library functions and definitions 30 #include "malloc-pc.h" 40 /*** Recognized AHCI Device Types ***/ 44 /*** AHCI/HBA Register Offsets and Bitmasks ***/ 308 /* AHCI Command Header Flags & Masks*/ 320 #define ATA_DEVICE_MAGIC 0xA0 /* used in ata1-3 */ 349 * Generic FIS structure. 358 * Register device-to-host FIS structure. 380 * Register device-to-host FIS structure; 405 * Register host-to-device FIS structure. [all …]
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H A D | meson.build | 9 'libqos-malloc.c', 11 'sdhci-cmd.c', 14 'malloc-spapr.c', 15 'libqos-spapr.c', 17 'pci-spapr.c', 20 'pci-pc.c', 21 'malloc-pc.c', 22 'libqos-pc.c', 23 'ahci.c', 31 'i2c-imx.c', [all …]
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/openbmc/u-boot/drivers/ata/ |
H A D | dwc_ahci.c | 1 // SPDX-License-Identifier: GPL-2.0+ 13 #include <ahci.h> 18 #include <generic-phy.h> 37 priv->base = map_physmem(devfdt_get_addr(dev), sizeof(void *), in dwc_ahci_ofdata_to_platdata() 42 priv->wrapper_base = map_physmem(addr, sizeof(void *), in dwc_ahci_ofdata_to_platdata() 45 priv->wrapper_base = NULL; in dwc_ahci_ofdata_to_platdata() 57 ret = generic_phy_get_by_name(dev, "sata-phy", &phy); in dwc_ahci_probe() 75 if (priv->wrapper_base) { in dwc_ahci_probe() 79 writel(val, priv->wrapper_base + TI_SATA_SYSCONFIG); in dwc_ahci_probe() 82 return ahci_probe_scsi(dev, (ulong)priv->base); in dwc_ahci_probe() [all …]
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/openbmc/linux/include/dt-bindings/ata/ |
H A D | ahci.h | 1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 3 * This header provides constants for most AHCI bindings. 9 /* Host Bus Adapter generic platform capabilities */ 13 /* Host Bus Adapter port-specific platform capabilities */
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/openbmc/linux/arch/mips/boot/dts/brcm/ |
H A D | bcm7346.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <163125000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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H A D | bcm7435.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <175625000>; 42 cpu_intc: interrupt-controller { 43 #address-cells = <0>; 44 compatible = "mti,cpu-interrupt-controller"; 46 interrupt-controller; [all …]
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H A D | bcm7425.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <163125000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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H A D | bcm7360.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <375000000>; 24 cpu_intc: interrupt-controller { 25 #address-cells = <0>; 26 compatible = "mti,cpu-interrupt-controller"; 28 interrupt-controller; [all …]
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H A D | bcm7362.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <375000000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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/openbmc/qemu/tests/qtest/fuzz/ |
H A D | generic_fuzz_configs.h | 2 * Generic Virtual-Device Fuzzing Target Configs 10 * See the COPYING file in the top-level directory. 23 g_autofree char *tmpdir = g_dir_make_tmp("qemu-fuzz.XXXXXX", NULL); in generic_fuzzer_virtio_9p_args() 26 return g_strdup_printf("-machine q35 -nodefaults " in generic_fuzzer_virtio_9p_args() 27 "-device virtio-9p,fsdev=hshare,mount_tag=hshare " in generic_fuzzer_virtio_9p_args() 28 "-fsdev local,id=hshare,path=%s,security_model=mapped-xattr," in generic_fuzzer_virtio_9p_args() 34 .name = "virtio-net-pci-slirp", 35 .args = "-M q35 -nodefaults " 36 "-device virtio-net,netdev=net0 -netdev user,id=net0", 39 .name = "virtio-blk", [all …]
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/openbmc/linux/arch/arm64/boot/dts/socionext/ |
H A D | uniphier-pxs3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/thermal/thermal.h> 14 compatible = "socionext,uniphier-pxs3"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 20 #address-cells = <2>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/amd/ |
H A D | amd-seattle-soc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 10 interrupt-parent = <&gic0>; 11 #address-cells = <2>; 12 #size-cells = <2>; 14 gic0: interrupt-controller@e1101000 { 15 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 16 interrupt-controller; 17 #interrupt-cells = <3>; 18 #address-cells = <2>; 19 #size-cells = <2>; [all …]
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