| /openbmc/linux/drivers/fpga/ |
| H A D | fpga-bridge.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Bridge Framework Driver
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 #include <linux/fpga/fpga-bridge.h>
23 * fpga_bridge_enable - Enable transactions on the bridge
25 * @bridge: FPGA bridge
29 int fpga_bridge_enable(struct fpga_bridge *bridge) in fpga_bridge_enable() argument
31 dev_dbg(&bridge->dev, "enable\n"); in fpga_bridge_enable()
33 if (bridge->br_ops && bridge->br_ops->enable_set) in fpga_bridge_enable()
34 return bridge->br_ops->enable_set(bridge, 1); in fpga_bridge_enable()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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| H A D | altera-hps2fpga.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
9 * Signed-off-by: Anatolij Gustschin <agust@denx.de>
14 * processor system (HPS) and the embedded FPGA.
17 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
19 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
23 #include <linux/fpga/fpga-bridge.h>
49 static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) in alt_hps2fpga_enable_show() argument
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| H A D | altera-fpga2sdram.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
12 * The bridge contains 4 read ports, 4 write ports, and 6 command ports.
15 * nor can the FPGA access the SDRAM during reconfiguration. This driver does
21 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
23 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
26 #include <linux/fpga/fpga-bridge.h>
56 static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge) in alt_fpga2sdram_enable_show() argument
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| H A D | dfl-fme-br.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Bridge Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-bridge.h>
20 #include "dfl-fme-pr.h"
28 static int fme_bridge_enable_set(struct fpga_bridge *bridge, bool enable) in fme_bridge_enable_set() argument
30 struct fme_br_priv *priv = bridge->priv; in fme_bridge_enable_set()
34 if (!priv->port_pdev) { in fme_bridge_enable_set()
35 port_pdev = dfl_fpga_cdev_find_port(priv->pdata->cdev, in fme_bridge_enable_set()
36 &priv->pdata->port_id, in fme_bridge_enable_set()
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| H A D | dfl-fme-pr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
24 * struct dfl_fme_region - FME fpga region data structure
26 * @region: platform device of the FPGA region.
37 * struct dfl_fme_region_pdata - platform data for FME region platform device.
39 * @mgr: platform device of the FPGA manager.
40 * @br: platform device of the FPGA bridge.
50 * struct dfl_fme_bridge - FME fpga bridge data structure
52 * @br: platform device of the FPGA bridge.
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| H A D | of-fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Device Tree support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
22 { .compatible = "fpga-region", },
28 * of_fpga_region_find - find FPGA region
29 * @np: device node of FPGA Region
31 * Caller will need to put_device(®ion->dev) when done.
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| H A D | dfl-fme-pr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga-bridge.h>
25 #include <linux/fpga/fpga-region.h>
26 #include <linux/fpga-dfl.h>
29 #include "dfl-fme.h"
30 #include "dfl-fme-pr.h"
37 list_for_each_entry(fme_region, &fme->region_list, node) in dfl_fme_region_find_by_port_id()
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| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-$(CONFIG_FPGA) += fpga-mgr.o
9 # FPGA Manager Drivers
10 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
12 obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
13 obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
14 obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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| H A D | xilinx-pr-decoupler.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
15 #include <linux/fpga/fpga-bridge.h>
34 writel(val, d->io_base + offset); in xlnx_pr_decoupler_write()
40 return readl(d->io_base + offset); in xlnx_pr_decouple_read()
43 static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable) in xlnx_pr_decoupler_enable_set() argument
46 struct xlnx_pr_decoupler_data *priv = bridge->priv; in xlnx_pr_decoupler_enable_set()
48 err = clk_enable(priv->clk); in xlnx_pr_decoupler_enable_set()
57 clk_disable(priv->clk); in xlnx_pr_decoupler_enable_set()
62 static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge) in xlnx_pr_decoupler_enable_show() argument
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| H A D | altera-freeze-bridge.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Freeze Bridge Controller
13 #include <linux/fpga/fpga-bridge.h>
44 struct device *dev = priv->dev; in altera_freeze_br_req_ack()
45 void __iomem *csr_illegal_req_addr = priv->base_addr + in altera_freeze_br_req_ack()
48 int ret = -ETIMEDOUT; in altera_freeze_br_req_ack()
62 ret = -EINVAL; in altera_freeze_br_req_ack()
66 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET); in altera_freeze_br_req_ack()
70 ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET); in altera_freeze_br_req_ack()
78 } while (timeout--); in altera_freeze_br_req_ack()
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| /openbmc/linux/include/linux/fpga/ |
| H A D | fpga-bridge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
12 * struct fpga_bridge_ops - ops for low level FPGA bridge drivers
13 * @enable_show: returns the FPGA bridge's status
14 * @enable_set: set an FPGA bridge as enabled or disabled
15 * @fpga_bridge_remove: set FPGA into a specific state during driver remove
19 int (*enable_show)(struct fpga_bridge *bridge);
20 int (*enable_set)(struct fpga_bridge *bridge, bool enable);
21 void (*fpga_bridge_remove)(struct fpga_bridge *bridge);
26 * struct fpga_bridge_info - collection of parameters an FPGA Bridge
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| H A D | fpga-mgr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FPGA Framework
5 * Copyright (C) 2013-2016 Altera Corporation
18 * enum fpga_mgr_states - fpga framework states
20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
22 * @FPGA_MGR_STATE_RESET: FPGA in reset state
25 * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
27 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
29 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
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| /openbmc/linux/Documentation/driver-api/fpga/ |
| H A D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge - The FPGA Bridge structure
8 * struct fpga_bridge_ops - Low level Bridge driver ops
9 * __fpga_bridge_register() - Create and register a bridge
10 * fpga_bridge_unregister() - Unregister a bridge
13 the module that registers the FPGA bridge as the owner.
15 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
18 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
21 .. kernel-doc:: drivers/fpga/fpga-bridge.c
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| H A D | fpga-region.rst | 1 FPGA Region
5 --------
7 This document is meant to be a brief overview of the FPGA region API usage. A
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
22 An fpga-region can be set up to know the following things:
24 * which FPGA manager to use to do the programming
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| H A D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
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| /openbmc/linux/Documentation/devicetree/bindings/fpga/ |
| H A D | fpga-region.txt | 1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
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| H A D | altera-hps2fpga-bridge.txt | 1 Altera FPGA/HPS Bridge Driver
4 - regs : base address and size for AXI bridge module
5 - compatible : Should contain one of:
6 "altr,socfpga-lwhps2fpga-bridge",
7 "altr,socfpga-hps2fpga-bridge", or
8 "altr,socfpga-fpga2hps-bridge"
9 - resets : Phandle and reset specifier for this bridge's reset
10 - clocks : Clocks used by this module.
12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
15 fpga_bridge0: fpga-bridge@ff400000 {
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| H A D | altera-fpga2sdram-bridge.txt | 1 Altera FPGA To SDRAM Bridge Driver
4 - compatible : Should contain "altr,socfpga-fpga2sdram-bridge"
6 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
9 fpga_bridge3: fpga-bridge@ffc25080 {
10 compatible = "altr,socfpga-fpga2sdram-bridge";
12 bridge-enable = <0>;
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| H A D | xlnx,pr-decoupler.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
14 decouplers/fpga bridges. The controller can decouple/disable the bridges
15 which prevents signal changes from passing through the bridge. The controller
17 bridge normally.
19 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
21 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
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| H A D | fpga-bridge.txt | 1 FPGA Bridge Device Tree Binding
4 - bridge-enable : 0 if driver should disable bridge at startup
5 1 if driver should enable bridge at startup
6 Default is to leave bridge in current state.
9 fpga_bridge3: fpga-bridge@ffc25080 {
10 compatible = "altr,socfpga-fpga2sdram-bridge";
12 bridge-enable = <0>;
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| H A D | altera-freeze-bridge.txt | 1 Altera Freeze Bridge Controller Driver
3 The Altera Freeze Bridge Controller manages one or more freeze bridges.
5 changes from passing through the bridge. The controller can also
7 bridge normally.
10 - compatible : Should contain "altr,freeze-bridge-controller"
11 - regs : base address and size for freeze bridge module
13 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
16 freeze-controller@100000450 {
17 compatible = "altr,freeze-bridge-controller";
19 bridge-enable = <0>;
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| /openbmc/linux/drivers/fpga/tests/ |
| H A D | fpga-region-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
11 #include <linux/fpga/fpga-bridge.h>
12 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/fpga/fpga-region.h>
30 struct fpga_bridge *bridge; member
40 struct mgr_stats *stats = mgr->priv; in op_write()
42 stats->write_count++; in op_write()
48 * Fake FPGA manager that implements only the write op to count the number
57 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
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| H A D | fpga-bridge-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Bridge
12 #include <linux/fpga/fpga-bridge.h>
21 struct fpga_bridge *bridge; member
26 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
28 struct bridge_stats *stats = bridge->priv; in op_enable_set()
30 stats->enable = enable; in op_enable_set()
36 * Fake FPGA bridge that implements only the enable_set op to track
44 * register_test_bridge() - Register a fake FPGA bridge for testing.
47 * Return: Context of the newly registered FPGA bridge.
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| /openbmc/u-boot/arch/arm/mach-socfpga/ |
| H A D | misc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
32 { "fpga", "FPGA (HPS2FPGA Bridge)", },
44 return -EINVAL; in dram_init()
63 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
65 writel(0x0, &pl310->pl310_tag_latency_ctrl); in v7_outer_cache_enable()
66 writel(0x10, &pl310->pl310_data_latency_ctrl); in v7_outer_cache_enable()
69 setbits_le32(&pl310->pl310_aux_ctrl, in v7_outer_cache_enable()
75 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
81 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_disable()
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