Searched +full:fpga +full:- +full:bridge (Results 1 – 25 of 34) sorted by relevance
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1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>32 { "fpga", "FPGA (HPS2FPGA Bridge)", },44 return -EINVAL; in dram_init()63 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()65 writel(0x0, &pl310->pl310_tag_latency_ctrl); in v7_outer_cache_enable()66 writel(0x10, &pl310->pl310_data_latency_ctrl); in v7_outer_cache_enable()69 setbits_le32(&pl310->pl310_aux_ctrl, in v7_outer_cache_enable()75 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()81 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_disable()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>24 #include <dt-bindings/reset/altr,rst-mgr.h>38 * FPGA programming support for SoC FPGA Cyclone V47 -1,95 printf("FPGA: Not Altera chip ID\n"); in socfpga_fpga_id()96 return -EINVAL; in socfpga_fpga_id()104 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); in socfpga_fpga_id()105 return -EINVAL; in socfpga_fpga_id()109 printf("FPGA: Altera %s, version 0x%01x\n", in socfpga_fpga_id()[all …]
1 // SPDX-License-Identifier: GPL-2.0+9 #include <asm/u-boot.h>34 const u32 bsel = readl(&sysmgr_regs->bootinfo); in spl_boot_device()37 case 0x1: /* FPGA (HPS2FPGA Bridge) */ in spl_boot_device()92 cm_basic_init(gd->fdt_blob); in board_init_f()103 config_dedicated_pins(gd->fdt_blob); in board_init_f()
1 // SPDX-License-Identifier: GPL-2.0+9 #include <asm/u-boot.h>34 const u32 bsel = readl(&sysmgr_regs->bootinfo); in spl_boot_device()37 case 0x1: /* FPGA (HPS2FPGA Bridge) */ in spl_boot_device()76 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in socfpga_pl310_clear()78 writel(0x111, &pl310->pl310_tag_latency_ctrl); in socfpga_pl310_clear()79 writel(0x121, &pl310->pl310_data_latency_ctrl); in socfpga_pl310_clear()82 setbits_le32(&pl310->pl310_aux_ctrl, in socfpga_pl310_clear()88 ena = readl(&pl310->pl310_ctrl); in socfpga_pl310_clear()93 * entirely in L1 I-cache to avoid any bus traffic through in socfpga_pl310_clear()[all …]
1 .. _MIPS-System-emulator:4 --------------------6 Four executables cover simulation of 32 and 64-bit MIPS systems in both7 endian options, ``qemu-system-mips``, ``qemu-system-mipsel``8 ``qemu-system-mips64`` and ``qemu-system-mips64el``. Five different11 - The MIPS Malta prototype board \"malta\"13 - An ACER Pica \"pica61\". This machine needs the 64-bit emulator.15 - MIPS emulator pseudo board \"mipssim\"17 - A MIPS Magnum R4000 machine \"magnum\". This machine needs the18 64-bit emulator.[all …]
16 orgnising devices in U-Boot. For PCI, driver model keeps track of55 bool "Generic ECAM-based PCI host controller support"59 Say Y here if you want to enable support for generic ECAM-based63 bool "Enable Armada-8K PCIe driver (DesignWare core)"68 Armada-8K SoCs. The PCIe controller on Armada-8K is based on99 support to work (e.g. beaver, jetson-tk1).102 bool "Xilinx AXI Bridge for PCI Express"105 Enable support for the Xilinx AXI bridge for PCI express, an IP block117 bool "Intel FPGA PCIe support"121 FPGA, example Stratix 10.
1 // SPDX-License-Identifier: GPL-2.03 * Intel FPGA PCIe host controller driver5 * Copyright (C) 2013-2018 Intel Corporation. All rights reserved38 ((pcie->hip_base) + (reg) + (1 << 20))42 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \47 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \52 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))63 ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)69 * struct intel_fpga_pcie - Intel FPGA PCIe controller state74 * first_busno stores the bus number of the PCIe root-port[all …]
1 // SPDX-License-Identifier: BSD-3-Clause24 clrsetbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_set_cd_ratio()29 /* Start the FPGA programming by initialize the FPGA Manager */35 msel = readl(&fpgamgr_regs->stat); in fpgamgr_program_init()44 setbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()59 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()74 /* To enable FPGA Manager configuration */ in fpgamgr_program_init()75 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()77 /* To enable FPGA Manager drive over configuration line */ in fpgamgr_program_init()78 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_init()[all …]
1 // SPDX-License-Identifier: GPL-2.037 reg = readl(&fpga_manager_base->imgcfg_stat); in fpgamgr_get_msel()47 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()50 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()56 return (readl(&fpga_manager_base->imgcfg_stat) & in is_fpgamgr_user_mode()62 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, in wait_for_user_mode()69 return (readl(&fpga_manager_base->imgcfg_stat) & in is_fpgamgr_early_user_mode()81 cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) & in fpgamgr_wait_early_user_mode()90 return -ETIMEDOUT; in fpgamgr_wait_early_user_mode()105 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */34 "update_filename=u-boot-with-spl.sfp\0" \45 "load_fpga=" /* Load FPGA bitstream */ \47 "fpga load 0 $loadaddr $filesize ; " \48 "bridge enable ; " \84 "if test -e mmc 0:2 ${bootscript} ; then " \
1 /* SPDX-License-Identifier: GPL-2.0+ */14 #define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb"55 "setenv hostname vining-${unit_serial} ; " \78 "1m(u-boot)," \83 "-(rcvrfs)\0" /* Recovery */ \86 "-(userfs)\0" \87 "update_filename=u-boot-with-spl-dtb.sfp\0" \96 "load_fpga=" /* Load FPGA bitstream */ \98 "fpga load 0 $loadaddr $filesize ; " \99 "bridge enable ; " \
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.16 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */18 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */76 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable78 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable80 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable81 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable88 * Localbus non-cacheable[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.27 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */129 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable130 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable131 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable136 * Localbus non-cacheable137 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.36 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */38 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */63 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */132 * Memory map -- xxx -this is wrong, needs updating135 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable136 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable137 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */3 * Copyright 2007-2011 Freescale Semiconductor, Inc.36 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */39 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */50 * L2CR setup -- make sure this is right for your board!64 * Base addresses -- Note these are effective addresses where the135 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */144 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */191 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"62 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */68 * Memory space is mapped 1-1, but I/O space must start from 0.248 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \351 - GENERATED_GBL_DATA_SIZE)[all …]
2 * bonito north bridge support4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)9 * Contributions after 2012-01-13 are licensed under the terms of the14 * fuloong 2e mini pc has a bonito north bridge.23 * In bonito north bridge, pci slot = IDSEL bit - 12.25 * pci slot = 17-12=531 * qemu also uses pci address for north bridge to access pci config register.38 * north bridge address to pci address.44 #include "qemu/error-report.h"48 #include "hw/pci-host/bonito.h"[all …]
4 * Copyright (c) 2006-2009 CodeSourcery.18 #include "hw/qdev-properties.h"59 * -------------------------------116 if (s->realview) { in pci_vpb_update_window()120 offset = s->imap[i] & ~(s->mem_win_size[i] - 1); in pci_vpb_update_window()123 offset = s->imap[i] << 28; in pci_vpb_update_window()125 memory_region_set_alias_offset(&s->pci_mem_window[i], offset); in pci_vpb_update_window()146 .name = "versatile-pci",189 int win = (addr - PCI_IMAP0) >> 2; in pci_vpb_reg_write()190 s->imap[win] = val; in pci_vpb_reg_write()[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR X113 * Copyright (C) 2016-2017 Intel Corporation5 *<auto-generated>11 *</auto-generated>17 #address-cells = <1>;18 #size-cells = <1>;22 cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */27 u-boot,dm-pre-reloc;28 #address-cells = <1>;29 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+6 #include <dt-bindings/reset/altr,rst-mgr.h>9 #address-cells = <1>;10 #size-cells = <1>;22 #address-cells = <1>;23 #size-cells = <0>;24 enable-method = "altr,socfpga-smp";27 compatible = "arm,cortex-a9";30 next-level-cache = <&L2>;33 compatible = "arm,cortex-a9";[all …]
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4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {28 "description": "The available OEM-specific actions for this resource.",29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {92 "description": "The Gen-Z related properties for the entity.",93 … "longDescription": "This property shall contain the Gen-Z related properties for the entity.",107 …operties contained in this object shall conform to the Redfish Specification-described requirement…113 "pattern": "^0[xX](([a-fA-F]|[0-9]){2}){3}$",[all …]
30 #include "qemu/guest-random.h"35 #include "hw/char/serial-mm.h"51 #include "qemu/host-utils.h"56 #include "qemu/error-report.h"60 #include "hw/qdev-clock.h"82 MemoryRegion iomem_lo; /* 0 - 0x900 */83 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */97 #define TYPE_MIPS_MALTA "mips-malta"114 /* Malta FPGA */120 for (i = 7 ; i >= 0 ; i--) { in malta_fpga_update_display_leds()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */12 * drivers and board-specific code within U-Boot. It aims to reduce the13 * amount of FDT munging required within U-Boot itself, so that driver code27 #define FDT_ADDR_T_NONE (-1U)32 #define FDT_ADDR_T_NONE (-1U)59 * be equal to: end - start + 1.93 * t: is 1 if the address is aliased (for non-relocatable I/O) below 1MB96 * bbbbbbbb: is the 8-bit Bus Number97 * ddddd: is the 5-bit Device Number98 * fff: is the 3-bit Function Number[all …]
1 // SPDX-License-Identifier: GPL-2.0+30 * good reason why driver-model conversion is infeasible. Examples include36 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),37 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),38 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),39 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),40 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),42 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),43 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),44 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),[all …]