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/openbmc/linux/arch/x86/um/
H A Dtls_32.c99 * Actually, now if it wasn't flushed it gets cleared and in load_TLS()
100 * flushed to the host, which will clear it. in load_TLS()
103 if (!curr->flushed) { in load_TLS()
112 if (!(flags & O_FORCE) && curr->flushed) in load_TLS()
119 curr->flushed = 1; in load_TLS()
127 * present desc's, only if they haven't been flushed.
142 if (curr->flushed) in needs_TLS_update()
151 * On a newly forked process, the TLS descriptors haven't yet been flushed. So
164 * will remain as flushed as it was. in clear_flushed_tls()
169 curr->flushed = 0; in clear_flushed_tls()
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dsecurity_features.h50 // The L1-D cache can be flushed with ori r30,r30,0
53 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
76 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
79 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
94 // The L1-D cache should be flushed when entering the kernel
97 // The L1-D cache should be flushed after user accesses from the kernel
/openbmc/qemu/include/exec/
H A Dexec-all.h63 * @cpu: CPU whose TLB should be flushed
64 * @addr: virtual address of page to be flushed
73 * @addr: virtual address of page to be flushed
79 * translations using the flushed TLBs.
84 * @cpu: CPU whose TLB should be flushed
99 * translations using the flushed TLBs.
104 * @cpu: CPU whose TLB should be flushed
105 * @addr: virtual address of page to be flushed
116 * @addr: virtual address of page to be flushed
123 * translations using the flushed TLBs.
[all …]
/openbmc/linux/mm/
H A Dpercpu-vm.c117 * @chunk: chunk the regions to be flushed belongs to
118 * @page_start: page index of the first page to be flushed
119 * @page_end: page index of the last page to be flushed + 1
174 * @chunk: pcpu_chunk the regions to be flushed belong to
175 * @page_start: page index of the first page to be flushed
176 * @page_end: page index of the last page to be flushed + 1
245 * @chunk: pcpu_chunk the regions to be flushed belong to
246 * @page_start: page index of the first page to be flushed
247 * @page_end: page index of the last page to be flushed + 1
/openbmc/qemu/scripts/qemu-guest-agent/fsfreeze-hook.d/
H A Dmysql-flush.sh.sample26 # wait until every block is flushed
31 # for InnoDB, wait until every log is flushed
40 LOG_FLUSHED=$(grep 'Log flushed up to' $INNODB_STATUS |\
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Difu.json57 "PublicDescription": "Thread flushed due to TLB miss",
60 "BriefDescription": "Thread flushed due to TLB miss"
63 "PublicDescription": "Thread flushed due to reasons other than TLB miss",
66 "BriefDescription": "Thread flushed due to reasons other than TLB miss"
/openbmc/linux/arch/x86/lib/
H A Dusercopy_64.c48 unsigned long flushed, dest = (unsigned long) dst; in __copy_user_flushcache() local
72 flushed = dest - (unsigned long) dst; in __copy_user_flushcache()
73 if (size > flushed && !IS_ALIGNED(size - flushed, 8)) in __copy_user_flushcache()
/openbmc/linux/tools/testing/selftests/net/forwarding/
H A Dbridge_locked_port.sh270 # Check that locked FDB entries are flushed from a port when MAB is disabled.
299 # FDB entry was flushed.
303 check_err $? "Regular FDB entry on first port was flushed after disabling MAB"
306 check_err $? "Regular FDB entry on second port was flushed after disabling MAB"
309 check_fail $? "Locked FDB entry on first port was not flushed after disabling MAB"
312 check_err $? "Locked FDB entry on second port was flushed after disabling MAB"
/openbmc/linux/tools/testing/selftests/drivers/net/dsa/
H A Dbridge_locked_port.sh270 # Check that locked FDB entries are flushed from a port when MAB is disabled.
299 # FDB entry was flushed.
303 check_err $? "Regular FDB entry on first port was flushed after disabling MAB"
306 check_err $? "Regular FDB entry on second port was flushed after disabling MAB"
309 check_fail $? "Locked FDB entry on first port was not flushed after disabling MAB"
312 check_err $? "Locked FDB entry on second port was flushed after disabling MAB"
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dgen2_engine_cs.c52 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is in gen4_emit_flush_rcs()
53 * also flushed at 2d versus 3d pipeline switches. in gen4_emit_flush_rcs()
57 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if in gen4_emit_flush_rcs()
58 * MI_READ_FLUSH is set, and is always flushed on 965. in gen4_emit_flush_rcs()
73 * are flushed at any MI_FLUSH. in gen4_emit_flush_rcs()
/openbmc/linux/arch/x86/um/asm/
H A Dprocessor_32.h17 unsigned flushed:1; member
30 { .present = 0, .flushed = 0 } }, \
/openbmc/linux/include/linux/
H A Dmm_types_task.h57 * will be flushed on all CPUs by the time that arch_tlbbatch_flush()
67 * flushed before IO is initiated or a stale TLB entry potentially
/openbmc/linux/drivers/infiniband/hw/cxgb4/
H A Dcq.c205 int flushed = 0; in c4iw_flush_rq() local
212 flushed++; in c4iw_flush_rq()
214 return flushed; in c4iw_flush_rq()
240 int flushed = 0; in c4iw_flush_sq() local
252 swsqe->flushed = 1; in c4iw_flush_sq()
257 flushed++; in c4iw_flush_sq()
261 wq->sq.flush_cidx += flushed; in c4iw_flush_sq()
264 return flushed; in c4iw_flush_sq()
291 swsqe->flushed = 1; in flush_completed_wrs()
362 if (qhp->wq.flushed == 1) in c4iw_flush_hw_cq()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_ctl.h51 * CTL registers need to be flushed after calling this function
63 * These masks are used to specify which block(s) need to be flushed
/openbmc/linux/drivers/net/ppp/
H A Dppp_mppe.c297 * set the FLUSHED bit. This is contrary to RFC 3078, sec. 3.1. in mppe_init()
439 int flushed = MPPE_BITS(ibuf) & MPPE_BIT_FLUSHED; in mppe_decompress() local
476 if (!state->stateful && !flushed) { in mppe_decompress()
477 printk(KERN_DEBUG "mppe_decompress[%d]: FLUSHED bit not set in " in mppe_decompress()
482 if (state->stateful && ((ccount & 0xff) == 0xff) && !flushed) { in mppe_decompress()
483 printk(KERN_DEBUG "mppe_decompress[%d]: FLUSHED bit not set on " in mppe_decompress()
522 if (!flushed) { in mppe_decompress()
547 if (flushed) in mppe_decompress()
/openbmc/linux/arch/csky/abiv2/
H A Dcacheflush.c75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
82 * flushed. in flush_icache_mm_range()
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Dpipeline.json58 "BriefDescription": "Fraction of dispatched ops that were flushed due to branch mispredicts.",
65 …"BriefDescription": "Fraction of dispatched ops that were flushed due to pipeline restarts (resync…
/openbmc/linux/drivers/gpu/drm/
H A Ddrm_cache.c74 mb(); /*Also used after CLFLUSH so that all cache is flushed*/ in drm_cache_flush_clflush()
80 * @pages: List of pages to be flushed.
137 mb(); /*Make sure that all cache line entry is flushed*/ in drm_clflush_sg()
171 mb(); /*Ensure that every data cache line entry is flushed*/ in drm_clflush_virt_range()
/openbmc/linux/include/uapi/drm/
H A Dv3d_drm.h130 * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
131 * each CL executes. The VCD cache should be flushed (if necessary)
133 * flushed by the time the render done IRQ happens, which is the
135 * possible using TMU writes) must be flushed by the caller using the
/openbmc/linux/arch/x86/kernel/acpi/
H A Dcstate.c40 * And caches should not be flushed by software while in acpi_processor_power_init_bm_check()
79 * And caches should not be flushed by software while in acpi_processor_power_init_bm_check()
93 * should not be flushed by software while entering C3 in acpi_processor_power_init_bm_check()
/openbmc/linux/arch/riscv/mm/
H A Dcacheflush.c49 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
56 * flushed. in flush_icache_mm()
/openbmc/linux/Documentation/devicetree/bindings/arm/msm/
H A Dqcom,idle-state.txt45 be flushed in s/w, before powering down the core.
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_top.h35 * @split_flush_en: Allows both the paths to be flushed when master path is
36 * flushed
/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c224 printf("ERR: D-cache not flushed\n"); in dcache_disable()
251 printf("ERR: D-cache not flushed\n"); in flush_dcache_range()
258 printf("ERR: D-cache not flushed\n"); in flush_dcache_all()
/openbmc/linux/arch/x86/include/asm/
H A Dtlbbatch.h10 * the PFNs being flushed..

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