| /openbmc/linux/arch/mips/bcm63xx/ |
| H A D | clk.c | 23 unsigned int rate; member
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
56 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
79 * Ethernet MAC clocks: only relevant on 6358, silently enable misc
80 * clocks
92 if (clk->id == 0) in enetx_set()
355 .rate = (50 * 1000 * 1000),
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | common.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/reset-controller.h>
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
27 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) in qcom_find_freq() argument
32 if (!f->freq) in qcom_find_freq()
35 for (; f->freq; f++) in qcom_find_freq()
36 if (rate <= f->freq) in qcom_find_freq()
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mtk.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 /* struct mtk_pll_data - hardware-specific PLLs data */
45 * struct mtk_fixed_clk - fixed clocks
47 * @id: index of clocks
48 * @parent: index of parnet clocks
49 * @rate: fixed rate
54 unsigned long rate; member
60 .rate = _rate, \
64 * struct mtk_fixed_factor - fixed multiplier and divider clocks
66 * @id: index of clocks
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| /openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| H A D | clk-core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
37 * struct clk_ops - standard clock operations
39 * @set_rate: set the clock rate, see clk_set_rate().
40 * @get_rate: get the clock rate, see clk_get_rate().
41 * @round_rate: round a given clock rate, see clk_round_rate().
51 int (*set_rate)(struct clk *c, unsigned long rate);
53 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
61 unsigned long rate; /* in HZ */ member
63 /* programmable divider. 0 means fixed ratio to parent clock */
79 #define BAD_CLK_NAME ((const char *)-1)
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| /openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| H A D | clk-core.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
37 * struct clk_ops - standard clock operations
39 * @set_rate: set the clock rate, see clk_set_rate().
40 * @get_rate: get the clock rate, see clk_get_rate().
41 * @round_rate: round a given clock rate, see clk_round_rate().
51 int (*set_rate) (struct clk *c, unsigned long rate);
53 unsigned long (*round_rate) (struct clk *c, unsigned long rate);
61 unsigned long rate; /* in HZ */ member
63 /* programmable divider. 0 means fixed ratio to parent clock */
79 #define BAD_CLK_NAME ((const char *)-1)
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
20 * @lock: maintains exclusion between callbacks for a given clock-provider.
21 * @clk_data: holds clock related data like clk_hw* and number of clocks.
53 * struct samsung_fixed_rate_clock: information about fixed-rate clock
55 * @name: name of this fixed-rate clock.
57 * @flags: optional fixed-rate clock flags.
58 * @fixed-rate: fixed clock rate of this clock.
78 * struct samsung_fixed_factor_clock: information about fixed-factor clock
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | fixed-factor-clock.txt | 1 Binding for TI fixed factor rate clock sources.
3 Binding status: Unstable - ABI compatibility may be broken in the future
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
16 - clocks: parent clock.
19 - clock-output-names : from common clock binding.
20 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | fixed-factor-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - fixed-factor-clock
18 "#clock-cells":
21 clocks:
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| H A D | samsung,s5pv210-audss-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 All available clocks are defined as preprocessor macros in
17 include/dt-bindings/clock/s5pv210-audss.h header.
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| H A D | samsung,s5pv210-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
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| H A D | canaan,k210-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Kendryte K210 SoC clocks driver bindings. The clock
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
24 clocks:
27 Phandle of the SoC 26MHz fixed-rate oscillator clock.
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| H A D | samsung,exynos5410-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "fin_pll" - PLL input clock from XXTI
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | nvidia,tegra20-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
34 clocks:
40 dma-names:
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| H A D | nvidia,tegra20-spdif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Thierry Reding <treding@nvidia.com>
17 - Jon Hunter <jonathanh@nvidia.com>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
35 clocks:
38 clock-names:
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| H A D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | fixed-factor-clock.txt | 1 Binding for simple fixed factor rate clock sources.
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "fixed-factor-clock".
9 - #clock-cells : from common clock binding; shall be set to 0.
10 - clock-div: fixed divider.
11 - clock-mult: fixed multiplier.
12 - clocks: parent clock.
15 - clock-output-names : From common clock binding.
19 compatible = "fixed-factor-clock";
20 clocks = <&parentclk>;
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| /openbmc/linux/drivers/clk/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
68 generators of audio clocks.
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
105 This driver provides support for clocks that are controlled
115 This driver provides support for clocks that are controlled
129 be pre-programmed to support other configurations and features not yet
171 This driver supports the clocks on Bitmain BM1880 SoC.
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
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| /openbmc/linux/Documentation/sound/soc/ |
| H A D | clocking.rst | 10 ------------
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
22 DAI Clocks
23 ----------
30 runs at exactly the sample rate (LRC = Rate).
32 Bit Clock can be generated as follows:-
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
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| /openbmc/linux/drivers/clk/imgtec/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 Enable this to support the system & CPU clocks on the MIPS Boston
9 fixed rate clocks whose rate is determined by reading a platform
|
| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
23 /* Maximum number of parents our clocks have */
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | am33xx-clocks.dtsi | 12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
15 ti,bit-shift = <22>;
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
22 clocks = <&sys_clkin_ck>;
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | stratix10-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* fixed rate clocks */
15 /* fixed factor clocks */
21 /* PLL clocks */
26 /* Periph clocks */
61 /* Gate clocks */
|
| H A D | agilex-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* fixed rate clocks */
16 /* PLL clocks */
31 /* fixed factor clocks */
45 /* Gate clocks */
|
| /openbmc/linux/drivers/clk/davinci/ |
| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
24 #include <linux/platform_data/clk-davinci-pll.h>
80 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
87 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
91 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
97 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
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| /openbmc/u-boot/drivers/clk/altera/ |
| H A D | clk-arria10.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
27 /* Fixed divider */
42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream()
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
54 dev_err(clk->dev, "Invalid control register\n"); in socfpga_a10_clk_get_upstream()
55 return -EINVAL; in socfpga_a10_clk_get_upstream()
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