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/openbmc/linux/drivers/clk/tegra/
H A Dclk-periph-fixed.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
19 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_is_enabled() local
20 u32 mask = 1 << (fixed->num % 32), value; in tegra_clk_periph_fixed_is_enabled()
22 value = readl(fixed->base + fixed->regs->enb_reg); in tegra_clk_periph_fixed_is_enabled()
24 value = readl(fixed->base + fixed->regs->rst_reg); in tegra_clk_periph_fixed_is_enabled()
34 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_enable() local
35 u32 mask = 1 << (fixed->num % 32); in tegra_clk_periph_fixed_enable()
37 writel(mask, fixed->base + fixed->regs->enb_set_reg); in tegra_clk_periph_fixed_enable()
44 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_disable() local
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/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen2-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
60 val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; in cpg_z_clk_recalc_rate()
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H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
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H A Drcar-gen4-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
76 mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; in cpg_pll_clk_recalc_rate()
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/openbmc/linux/drivers/clk/
H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
26 unsigned long long int rate; in clk_factor_recalc_rate() local
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
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H A Dclk-fixed-rate.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
24 * parent - fixed parent. No clk_set_parent support
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/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h1 /* SPDX-License-Identifier: GPL-2.0+ */
37 * struct clk_ops - standard clock operations
39 * @set_rate: set the clock rate, see clk_set_rate().
40 * @get_rate: get the clock rate, see clk_get_rate().
41 * @round_rate: round a given clock rate, see clk_round_rate().
42 * @set_parent: set the clock's parent, see clk_set_parent().
51 int (*set_rate)(struct clk *c, unsigned long rate);
53 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
54 int (*set_parent)(struct clk *c, struct clk *parent);
58 struct clk *parent; member
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/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h1 /* SPDX-License-Identifier: GPL-2.0+ */
37 * struct clk_ops - standard clock operations
39 * @set_rate: set the clock rate, see clk_set_rate().
40 * @get_rate: get the clock rate, see clk_get_rate().
41 * @round_rate: round a given clock rate, see clk_round_rate().
42 * @set_parent: set the clock's parent, see clk_set_parent().
51 int (*set_rate) (struct clk *c, unsigned long rate);
53 unsigned long (*round_rate) (struct clk *c, unsigned long rate);
54 int (*set_parent) (struct clk *c, struct clk *parent);
58 struct clk *parent; member
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/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 /* struct mtk_pll_data - hardware-specific PLLs data */
45 * struct mtk_fixed_clk - fixed clocks
48 * @parent: index of parnet clocks
49 * @rate: fixed rate
53 const int parent; member
54 unsigned long rate; member
59 .parent = _parent, \
60 .rate = _rate, \
64 * struct mtk_fixed_factor - fixed multiplier and divider clocks
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
3 Binding status: Unstable - ABI compatibility may be broken in the future
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
16 - clocks: parent clock.
19 - clock-output-names : from common clock binding.
20 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
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/openbmc/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <clk-uclass.h>
19 #include <dt-bindings/clock/renesas-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
62 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_enable()
64 return renesas_clk_endisable(clk, priv->base, true); in gen2_clk_enable()
69 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_disable()
71 return renesas_clk_endisable(clk, priv->base, false); in gen2_clk_disable()
76 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_get_rate()
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/openbmc/linux/drivers/clk/samsung/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
20 * @lock: maintains exclusion between callbacks for a given clock-provider.
53 * struct samsung_fixed_rate_clock: information about fixed-rate clock
55 * @name: name of this fixed-rate clock.
56 * @parent_name: optional parent clock name.
57 * @flags: optional fixed-rate clock flags.
58 * @fixed-rate: fixed clock rate of this clock.
78 * struct samsung_fixed_factor_clock: information about fixed-factor clock
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/openbmc/linux/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
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/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_core_perf.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
16 * struct dpu_core_perf_params - definition of performance parameters
19 * @core_clk_rate: core clock rate request
28 * struct dpu_core_perf_tune - definition of performance tuning control
36 * struct dpu_core_perf - definition of core performance context
37 * @perf_cfg: Platform-specific performance configuration
38 * @core_clk_rate: current core clock rate
39 * @max_core_clk_rate: maximum allowable core clock rate
42 * @fix_core_clk_rate: fixed core clock request in Hz used in mode 2
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/openbmc/linux/drivers/clk/at91/
H A Dclk-audio-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Quentin Schulz <quentin.schulz@free-electrons.com>
9 * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
10 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
11 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
12 * asked rate.
15 * enable - clk_enable writes nd, fracr parameters and enables PLL
16 * rate - rate is adjustable.
17 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
18 * parent - fixed parent. No clk_set_parent support
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/openbmc/linux/drivers/clk/bcm/
H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
27 /* Produces a mask of set bits covering a range of a 32-bit value */
30 return ((1 << width) - 1) << shift; in bitfield_mask()
52 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
68 combined <<= div->u.s.frac_width; in scaled_div_build()
78 return (u64)div->u.fixed; in scaled_div_min()
89 return (u64)div->u.fixed; in scaled_div_max()
91 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
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/openbmc/linux/drivers/clk/davinci/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
24 #include <linux/platform_data/clk-davinci-pll.h>
80 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
87 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
91 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
97 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
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H A Dpll.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/clk-provider.h>
20 #define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */
23 #define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */
28 /** davinci_pll_clk_info - controller-specific PLL info
35 * @pllout_min_rate: Minimum allowable rate for PLLOUT
36 * @pllout_max_rate: Maximum allowable rate for PLLOUT
51 #define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */
53 #define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */
55 /** davinci_pll_sysclk_info - SYSCLKn-specific info
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/openbmc/u-boot/drivers/clk/
H A Dclk_fixed_factor.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
14 struct clk parent; member
24 uint64_t rate; in clk_fixed_factor_get_rate() local
25 struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev); in clk_fixed_factor_get_rate()
27 if (clk->id != 0) in clk_fixed_factor_get_rate()
28 return -EINVAL; in clk_fixed_factor_get_rate()
30 rate = clk_get_rate(&ff->parent); in clk_fixed_factor_get_rate()
31 if (IS_ERR_VALUE(rate)) in clk_fixed_factor_get_rate()
32 return rate; in clk_fixed_factor_get_rate()
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
40 dma-names:
42 - const: rx
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H A Dnvidia,tegra20-spdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Thierry Reding <treding@nvidia.com>
17 - Jon Hunter <jonathanh@nvidia.com>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
38 clock-names:
40 - const: out
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/openbmc/linux/drivers/clk/st/
H A Dclkgen-fsyn.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
186 { .name = "clk-s-d0-fs0-ch0", },
187 { .name = "clk-s-d0-fs0-ch1", },
188 { .name = "clk-s-d0-fs0-ch2", },
189 { .name = "clk-s-d0-fs0-ch3", },
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,s5pv210-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/s5pv210-audss.h header.
21 const: samsung,s5pv210-audss-clock
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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dfixed-factor-clock.txt1 Binding for simple fixed factor rate clock sources.
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "fixed-factor-clock".
9 - #clock-cells : from common clock binding; shall be set to 0.
10 - clock-div: fixed divider.
11 - clock-mult: fixed multiplier.
12 - clocks: parent clock.
15 - clock-output-names : From common clock binding.
19 compatible = "fixed-factor-clock";
21 #clock-cells = <0>;
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