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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
14 a phandle to the MDMA controller plus the following five integer cells:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
24 - items:
25 - enum:
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dwlf,arizona.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
17 - $ref: /schemas/spi/spi-peripheral-props.yaml
18 - $ref: /schemas/sound/wlf,arizona.yaml#
19 - $ref: /schemas/regulator/wlf,arizona.yaml#
20 - $ref: /schemas/extcon/wlf,arizona.yaml#
21 - if:
26 - cirrus,cs47l24
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/openbmc/qemu/scripts/simplebench/
H A Dbench-example.py27 """ Handle one "cell" of benchmarking table. """
32 # You may set the following five variables to correct values, to turn this
34 ssd_source = '/path-to-raw-source-image-at-ssd'
35 ssd_target = '/path-to-raw-target-image-at-ssd'
36 hdd_target = '/path-to-raw-source-image-at-hdd'
37 nbd_ip = 'nbd-ip-addr'
38 nbd_port = 'nbd-port-number'
40 # Test-cases are "rows" in benchmark resulting table, 'id' is a caption for
44 'id': 'ssd -> ssd',
49 'id': 'ssd -> hdd',
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rzg2l-cpg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
27 - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
28 - renesas,r9a07g044-cpg # RZ/G2{L,LC}
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/openbmc/linux/Documentation/devicetree/bindings/virtio/
H A Dpci-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: virtio-iommu device using the virtio-pci transport
10 - Jean-Philippe Brucker <jean-philippe@linaro.org>
13 When virtio-iommu uses the PCI transport, its programming interface is
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
20 virtio-iommu node doesn't have an "iommus" property, and is omitted from
21 the iommu-map property of the root complex.
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dpci.txt3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
36 PCI-PCI Bridge properties
37 -------------------------
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpamu.txt5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
31 - reg : <prop-encoded-array>
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/openbmc/linux/arch/powerpc/platforms/
H A DKconfig.cputype1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
18 There are five families of 32 bit PowerPC chips supported.
145 bool "Cell Broadband Engine"
256 default "cell" if CELL_CPU
282 default "-mtune=power10" if $(cc-option,-mtune=power10)
283 default "-mtune=power9" if $(cc-option,-mtune=power9)
284 default "-mtune=power8" if $(cc-option,-mtune=power8)
366 This option enables kernel support for larger than 32-bit physical
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/openbmc/linux/Documentation/admin-guide/
H A Dunicode.rst4 Last update: 2005-01-17, version 1.4
12 ------------
15 characters to fonts. By downloading a single Unicode-to-font table,
16 both the eight-bit character sets and UTF-8 mode are changed to use
19 This changes the semantics of the eight-bit character tables subtly.
25 LAT1_MAP Latin-1 (ISO 8859-1) ESC ( B
33 permits for example the use of block graphics even with a Latin-1 font
37 codes nor their uses match ISO 2022; Linux has two 8-bit codes (G0 and
38 G1), whereas ISO 2022 has four 7-bit codes (G0-G3).
41 U+F8FF has been reserved for OS-wide allocation (the Unicode Standard
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/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019-2022 MediaTek Inc.
18 #include <linux/arm-smccc.h>
23 #include <linux/media-bus-format.h>
24 #include <linux/nvmem-consumer.h>
33 #include <sound/hdmi-codec.h>
317 .name = "mtk-dp-registers",
330 ret = regmap_read(mtk_dp->regs, offset, &read_val); in mtk_dp_read()
332 dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n", in mtk_dp_read()
342 int ret = regmap_write(mtk_dp->regs, offset, val); in mtk_dp_write()
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/openbmc/u-boot/doc/
H A DREADME.x861 # SPDX-License-Identifier: GPL-2.0+
6 U-Boot on x86
9 This document describes the information about U-Boot running on x86 targets,
13 ------
14 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17 most of the low-level details.
19 U-Boot is a main bootloader on Intel Edison board.
21 U-Boot also supports booting directly from x86 reset vector, without coreboot.
23 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
26 - Bayley Bay CRB
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/openbmc/linux/include/uapi/linux/
H A Dbpf.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
21 #define BPF_DW 0x18 /* double word (64-bit) */
23 #define BPF_ATOMIC 0xc0 /* atomic memory ops - op type in immediate */
24 #define BPF_XADD 0xc0 /* exclusive add - legacy name */
32 #define BPF_TO_LE 0x00 /* convert to little-endian */
33 #define BPF_TO_BE 0x08 /* convert to big-endian */
51 #define BPF_CMPXCHG (0xf0 | BPF_FETCH) /* atomic compare-and-write */
69 /* BPF has 10 general purpose 64-bit registers and stack frame. */
111 BPF_CGROUP_ITER_DESCENDANTS_PRE, /* walk descendants in pre-order. */
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/openbmc/linux/tools/include/uapi/linux/
H A Dbpf.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
21 #define BPF_DW 0x18 /* double word (64-bit) */
23 #define BPF_ATOMIC 0xc0 /* atomic memory ops - op type in immediate */
24 #define BPF_XADD 0xc0 /* exclusive add - legacy name */
32 #define BPF_TO_LE 0x00 /* convert to little-endian */
33 #define BPF_TO_BE 0x08 /* convert to big-endian */
51 #define BPF_CMPXCHG (0xf0 | BPF_FETCH) /* atomic compare-and-write */
69 /* BPF has 10 general purpose 64-bit registers and stack frame. */
111 BPF_CGROUP_ITER_DESCENDANTS_PRE, /* walk descendants in pre-order. */
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