bindings/clock/renesas%2Crzg2l-cpg.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Geert Uytterhoeven <geert+renesas@glider.be>
13   On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
18     - The CPG block generates various core clocks,
19     - The Module Standby Mode block provides two functions:
27       - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
28       - renesas,r9a07g044-cpg # RZ/G2{L,LC}
29       - renesas,r9a07g054-cpg # RZ/V2L
30       - renesas,r9a09g011-cpg # RZ/V2M
38   clock-names:
44   '#clock-cells':
46       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
48         <dt-bindings/clock/r9a0*-cpg.h>,
49       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
50         a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
53   '#power-domain-cells':
56       can be power-managed through Module Standby should refer to the CPG device
57       node in their "power-domains" property, as documented by the generic PM
58       Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
61   '#reset-cells':
63       The single reset specifier cell must be the module number, as defined in
64       <dt-bindings/clock/r9a0*-cpg.h>.
68   - compatible
69   - reg
70   - clocks
71   - clock-names
72   - '#clock-cells'
73   - '#power-domain-cells'
74   - '#reset-cells'
79   - |
80     cpg: clock-controller@11010000 {
81             compatible = "renesas,r9a07g044-cpg";
84             clock-names = "extal";
85             #clock-cells = <2>;
86             #power-domain-cells = <0>;
87             #reset-cells = <1>;