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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml#
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
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H A Dstarfive,jh7110-mmc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: synopsys-dw-mshc-common.yaml#
17 - William Qiu <william.qiu@starfivetech.com>
21 const: starfive,jh7110-mmc
28 - description: biu clock
29 - description: ciu clock
31 clock-names:
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H A Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
33 clock-names:
35 - const: biu
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/openbmc/linux/drivers/iio/imu/inv_icm42600/
H A Dinv_icm42600_buffer.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * struct inv_icm42600_fifo - FIFO state variables
20 * @on: reference counter for FIFO on.
21 * @en: bits field of INV_ICM42600_SENSOR_* for FIFO EN bits.
22 * @period: FIFO internal period.
23 * @watermark: watermark configuration values for accel and gyro.
24 * @count: number of bytes in the FIFO data buffer.
25 * @nb: gyro, accel and total samples in the FIFO data buffer.
26 * @data: FIFO data buffer aligned for DMA (2kB + 32 bytes of read cache).
35 } watermark; member
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H A Dinv_icm42600.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
69 /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */
88 /* Low-Noise mode sensor data filter (3rd order filter by default) */
91 /* Low-Power mode sensor data filter (averaging) */
102 #define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1}
117 * struct inv_icm42600_state - driver state variables
129 * @buffer: data transfer buffer aligned for DMA.
130 * @fifo: FIFO management structure.
146 struct inv_icm42600_fifo fifo; member
190 /* all sensor data are 16 bits (2 registers wide) in big-endian */
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H A Dinv_icm42600_gyro.c1 // SPDX-License-Identifier: GPL-2.0-or-later
75 * IIO buffer data: size must be a power of 2 and timestamp aligned
92 /* 3-axis gyro + temperature */
97 /* enable gyroscope sensor and FIFO write */
109 mutex_lock(&st->lock); in inv_icm42600_gyro_update_scan_mode()
128 /* update data FIFO write */ in inv_icm42600_gyro_update_scan_mode()
129 ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); in inv_icm42600_gyro_update_scan_mode()
132 mutex_unlock(&st->lock); in inv_icm42600_gyro_update_scan_mode()
147 struct device *dev = regmap_get_device(st->map); in inv_icm42600_gyro_read_sensor()
153 if (chan->type != IIO_ANGL_VEL) in inv_icm42600_gyro_read_sensor()
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H A Dinv_icm42600_accel.c1 // SPDX-License-Identifier: GPL-2.0-or-later
75 * IIO buffer data: size must be a power of 2 and timestamp aligned
92 /* 3-axis accel + temperature */
97 /* enable accelerometer sensor and FIFO write */
109 mutex_lock(&st->lock); in inv_icm42600_accel_update_scan_mode()
128 /* update data FIFO write */ in inv_icm42600_accel_update_scan_mode()
129 ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); in inv_icm42600_accel_update_scan_mode()
132 mutex_unlock(&st->lock); in inv_icm42600_accel_update_scan_mode()
147 struct device *dev = regmap_get_device(st->map); in inv_icm42600_accel_read_sensor()
153 if (chan->type != IIO_ACCEL) in inv_icm42600_accel_read_sensor()
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dsf.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
10 /* Smart Fifo state */
19 /* Smart Fifo possible scenario */
32 /* smart FIFO default values */
39 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
51 /* SF Scenarios timers for BSS MAC configuration (aligned to 32 uSec) */
68 * struct iwl_sf_cfg_cmd - Smart Fifo configuration command.
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/openbmc/linux/drivers/iio/imu/st_lsm6dsx/
H A Dst_lsm6dsx_buffer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * STMicroelectronics st_lsm6dsx FIFO buffer library driver
5 * LSM6DS3/LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C:
6 * The FIFO buffer can be configured to store data from gyroscope and
8 * specific pattern based on 'FIFO data sets' (6 bytes each):
9 * - 1st data set is reserved for gyroscope data
10 * - 2nd data set is reserved for accelerometer data
11 * The FIFO pattern changes depending on the ODRs and decimation factors
12 * assigned to the FIFO data sets. The first sequence of data stored in FIFO
13 * buffer contains the data of all the enabled FIFO data sets
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/openbmc/linux/arch/powerpc/platforms/512x/
H A Dmpc512x_lpbfifo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * The driver for Freescale MPC512x LocalPlus Bus FIFO
6 * Copyright (C) 2013-2015 Alexander Popov <alex.popov@linux.com>.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
61 * mpc512x_lpbfifo_irq - IRQ handler for LPB FIFO
76 if (!req || req->dir == MPC512X_LPBFIFO_REQ_DIR_READ) { in mpc512x_lpbfifo_irq()
81 status = in_be32(&lpbfifo.regs->status); in mpc512x_lpbfifo_irq()
84 out_be32(&lpbfifo.regs->enable, in mpc512x_lpbfifo_irq()
89 out_be32(&lpbfifo.regs->status, MPC512X_SCLPC_SUCCESS); in mpc512x_lpbfifo_irq()
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/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_display.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 #include <linux/dma-buf.h>
11 #include <linux/media-bus-format.h>
31 /* TODO: implement FIFO C0 and FIFO C1 */
80 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
81 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
82 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
92 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
101 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_irq()
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio3 Contact: linux-iio@vger.kernel.org
11 Contact: linux-iio@vger.kernel.org
25 Contact: linux-iio@vger.kernel.org
31 Contact: linux-iio@vger.kernel.org
38 Contact: linux-iio@vger.kernel.org
44 The contents of the label are free-form, but there are some
51 * "proximity-wifi"
52 * "proximity-lte"
53 * "proximity-wifi-lte"
54 * "proximity-wifi-left"
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/openbmc/linux/drivers/net/usb/
H A Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
57 #define INT_STS_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
58 #define INT_STS_TDFO_ (0x00001000) /* TX Data FIFO Overrun */
65 #define RX_FIFO_FLUSH_ (0x00000001) /* Receive FIFO Flush */
71 #define TX_CFG_FIFO_FLUSH_ (0x00000001) /* Transmit FIFO Flush */
88 /* Receive FIFO Information Register */
90 #define RX_FIFO_INF_USED_ (0x0000FFFF) /* RX Data FIFO Used Space */
92 /* Transmit FIFO Information Register */
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/openbmc/linux/sound/soc/fsl/
H A Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
16 #include <linux/dma-mapping.h>
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
120 * Since each link descriptor has a 32-bit byte count field, we set
121 * period_bytes_max to the largest 32-bit number. We also have no maximum
137 .period_bytes_max = (u32) -1,
139 .periods_max = (unsigned int) -1,
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H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
13 // one FIFO which combines all valid receive slots. We cannot even select
16 // we receive in our (PCM-) data stream. The only chance we have is to
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
65 * order. The STX is a shift register, so all the bits need to be aligned
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/openbmc/linux/drivers/net/ethernet/broadcom/
H A Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
41 #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
42 #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
65 #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */
90 #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
110 #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */
113 #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */
120 #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */
121 #define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-fsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * FSI-attached I2C master algorithm
71 /* watermark register */
189 u32 mode = I2C_MODE_ENHANCED, extended_status, watermark; in fsi_i2c_dev_init() local
193 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, &interrupt); in fsi_i2c_dev_init()
198 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode); in fsi_i2c_dev_init()
202 rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &extended_status); in fsi_i2c_dev_init()
206 i2c->fifo_size = FIELD_GET(I2C_ESTAT_FIFO_SZ, extended_status); in fsi_i2c_dev_init()
207 watermark = FIELD_PREP(I2C_WATERMARK_HI, in fsi_i2c_dev_init()
208 i2c->fifo_size - I2C_FIFO_HI_LVL); in fsi_i2c_dev_init()
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/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/openbmc/linux/drivers/tty/serial/
H A Dserial-tegra.c1 // SPDX-License-Identifier: GPL-2.0
5 * High-speed serial driver for NVIDIA Tegra SoCs
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
16 #include <linux/dma-mapping.h>
56 * Tx fifo trigger level setting in tegra uart is in
79 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
80 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
83 * @fifo_mode_enable_status: Is FIFO mode enabled?
159 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
165 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
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/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/dma-mapping.h>
39 #include <linux/mmc/slot-gpio.h>
74 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
79 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
80 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
82 u32 des6; /* Lower 32-bits of Next Descriptor Address */
83 u32 des7; /* Upper 32-bits of Next Descriptor Address */
98 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
111 struct dw_mci_slot *slot = s->private; in dw_mci_req_show()
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/openbmc/linux/drivers/iio/adc/
H A Dat91-sama5d2_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/dma-mapping.h>
31 #include <linux/nvmem-consumer.h>
36 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
110 /* Interrupt Enable Register - TS X measurement ready */
112 /* Interrupt Enable Register - TS Y measurement ready */
114 /* Interrupt Enable Register - TS pressure measurement ready */
116 /* Interrupt Enable Register - Data ready */
118 /* Interrupt Enable Register - general overrun error */
120 /* Interrupt Enable Register - Pen detect */
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/openbmc/linux/include/linux/iio/
H A Diio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
39 * struct iio_chan_spec_ext_info - Extended channel info attribute
58 * struct iio_enum - Enum channel info attribute
89 * IIO_ENUM() - Initialize enum extended channel attribute
106 * IIO_ENUM_AVAILABLE() - Initialize enum available extended channel attribute
123 * struct iio_mount_matrix - iio mounting matrix
140 * IIO_MOUNT_MATRIX() - Initialize mount matrix extended channel attribute
153 * struct iio_event_spec - specification for a channel event
176 * struct iio_chan_spec - specification of a single channel
225 * iio_info->read_label() to override the label, which
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/openbmc/linux/drivers/spi/
H A Dspi-geni-qcom.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
16 #include <linux/soc/qcom/geni-se.h>
108 struct geni_se *se = &mas->se; in spi_slv_setup()
110 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); in spi_slv_setup()
111 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); in spi_slv_setup()
112 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); in spi_slv_setup()
113 dev_dbg(mas->dev, "spi slave setup done\n"); in spi_slv_setup()
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-trans.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
15 #include "iwl-debug.h"
16 #include "iwl-config.h"
18 #include "iwl-op-mode.h"
22 #include "fw/api/dbg-tlv.h"
23 #include "iwl-dbg-tlv.h"
26 * DOC: Transport layer - what is it ?
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/openbmc/linux/include/linux/
H A Dmm_types.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #include <linux/page-flags-layout.h>
46 * which is guaranteed to be aligned. If you use the same storage as
47 * page->mapping, you must restore it to NULL before freeing the page.
64 * double-word aligned. Because struct slab currently just reinterprets the
65 * bits of struct page, we align all struct pages to double-word boundaries,
66 * and ensure that 'freelist' is aligned within struct slab.
81 * avoid collision and false-positive PageTail().
87 * lruvec->lru_lock. Sometimes used as a generic list
105 /* See page-flags.h for PAGE_MAPPING_FLAGS */
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