Searched full:fec1 (Results 1 – 25 of 179) sorted by relevance
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108 u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */117 u8 podr_fec1h; /* FEC1 High Port Output Data Register */118 u8 podr_fec1l; /* FEC1 Low Port Output Data Register */131 u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */140 u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */141 u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */154 u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */163 u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */164 u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */177 u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */[all …]
128 puts("FEC MXS: Unable to init FEC1\n"); in board_eth_init()138 dev = eth_get_dev_by_name("FEC1"); in board_eth_init()140 puts("FEC MXS: Unable to get FEC1 device entry\n"); in board_eth_init()
43 object_property_set_uint(OBJECT(s), "fec1-phy-num", 2, &error_fatal); in mcimx6ul_evk_init()45 object_property_set_bool(OBJECT(s), "fec1-phy-connected", false, in mcimx6ul_evk_init()
33 &fec1 {87 pinctrl_fec1: fec1-grp {
101 &fec1 {421 pinctrl_fec1: fec1-grp {423 /* FEC1 uses MDIO bus from FEC2 */435 pinctrl_fec1_phy: fec1-phy-grp {620 pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp {
10 /delete-node/ &fec1;
12 ethernet0 = &fec1;
30 &fec1 {
20 &fec1 {
28 &fec1 {
25 &fec1 {
44 &fec1 {
441 bool "FEC1"446 int "FEC1 PHY"453 means that the PHY with address 4 is connected to FEC1478 means that the PHY with address 4 is connected to FEC1
22 &fec1 {
19 &fec1 {
7 &fec1 {
11 &fec1 {
151 * fec1 shares the some PINs with usdhc2.153 * Please disable usdhc2 to enable fec1155 &fec1 {
9 ethernet0 = &fec1;88 &fec1 {
97 &fec1 {133 ethernet = <&fec1>;
147 &fec1 {206 ethernet = <&fec1>;
108 &fec1 {144 ethernet = <&fec1>;
122 &fec1 {158 ethernet = <&fec1>;